Patents by Inventor Sheng-An Wang

Sheng-An Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105631
    Abstract: Embodiments provide a method of performing a carrier switch for a device wafer, attaching a second wafer and removing a first wafer. A buffer layer is deposited over the device wafer, buffer layer reducing the topography of the surface of the device wafer. After the carrier switch a film-on-wire layer is removed from the buffer layer and then the buffer layer is at least in part removed.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 28, 2024
    Inventors: Jeng-An Wang, Sheng-Chi Lin, Hao-Cheng Hou, Tsung-Ding Wang, Chien-Hsun Lee
  • Publication number: 20240105532
    Abstract: The present disclosure provides a chip packaging method and a chip packaging structure. The chip packaging method includes: providing an encapsulated grain and a packaging substrate, the encapsulated grain including a first hybrid bonding structure; wherein the packaging substrate includes a front side and a back side opposite to each other; a second hybrid bonding structure is formed on the front side of the packaging substrate and a connection pin is formed on the back side of the packing substrate; the second hybrid bonding structure and the connection pin are electrically connected through a third connecting metal column penetrating the packaging substrate; and bonding together the first hybrid bonding structure of the encapsulated grain and the second hybrid bonding structure of the packaging substrate by medium-to-medium and metal-to-metal aligned bonding such that the encapsulated grain is bonded to the packaging substrate.
    Type: Application
    Filed: December 31, 2022
    Publication date: March 28, 2024
    Inventors: Zhigang PAN, Ning WANG, Xiaoqin SUN, Peng SUN, Daohong YANG, Sheng HU, Guoliang YE
  • Publication number: 20240107250
    Abstract: A method for performing audio enhancement with aid of timing control includes: utilizing a UE to determine a first predetermined synchronization delay and notify a first earphone of the first predetermined synchronization delay, wherein a first DSP circuit in the first earphone is arranged to determine a synchronization point according to a first time point of a first event and the first predetermined synchronization delay for the first earphone; utilizing the UE to determine a second predetermined synchronization delay and notify a second earphone of the second predetermined synchronization delay, wherein a second DSP circuit in the second earphone is arranged to determine the synchronization point according to a second time point of a second event and the second predetermined synchronization delay for the second earphone; and utilizing the UE to receive first uplink audio data from the first earphone and receive second uplink audio data from the second earphone.
    Type: Application
    Filed: December 6, 2022
    Publication date: March 28, 2024
    Applicant: MEDIATEK INC.
    Inventors: Hsi-Hsien Chen, Yili Wang, Chia-Wei Tao, Sheng-Ming Wang
  • Patent number: 11941737
    Abstract: Embodiments of this application disclose an artificial intelligence-based (AI-based) animation character control method. When one animation character has a corresponding face customization base, and one animation character has no corresponding face customization base, the animation character having the face customization base may be used as a driving character, and the animation character having no face customization base may be used as a driven character.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: March 26, 2024
    Assignee: Tencent Technology (Shenzhen) Company Limited
    Inventors: Sheng Wang, Xing Ji, Zhantu Zhu, Xiangkai Lin, Linchao Bao
  • Patent number: 11940998
    Abstract: This disclosure provides a computer-implemented method, a computer system and a computer program product for database compression oriented to combinations of fields of a database record. One or more combinations of fields of a record of a database are determined that satisfy a frequency criterion indicating that access frequencies of the one or more combinations of fields are higher than an access frequency threshold. The record is reorganized based on the one or more combinations of fields to store fields of each combination of the one or more combinations of fields in a respective contiguous storage space. The reorganized record is compressed by applying a compression scheme to the one or more combinations of fields.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: March 26, 2024
    Assignee: International Business Machines Corporation
    Inventors: Ying Zhang, Xiaobo Wang, Shuo Li, Sheng Yan Sun
  • Patent number: 11940975
    Abstract: A computer-implemented method that includes receiving an ingestion request to ingest data to a database comprising physical shards and detecting that the ingestion request is directed to a first hotspot shard. The first hotspot shard has a contention level over a threshold value. The method also detects context characteristics within the data and generates a first virtual shard based on a first virtual shard key selected from the detected context characteristics. The first virtual shard virtually duplicates at least a portion of the first hotspot shard. The method also includes ingesting the data to the first virtual shard.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: March 26, 2024
    Assignee: International Business Machines Corporation
    Inventors: Shuo Li, Peng Hui Jiang, Xiaobo Wang, Sheng Yan Sun
  • Patent number: 11940732
    Abstract: Coating compositions comprise: a curable compound comprising: a core chosen from a C6 carbocyclic aromatic ring, a C2-5 heterocyclic aromatic ring, a C9-30 fused carbocyclic aromatic ring system, a C4-30 fused heterocyclic aromatic ring system, C1-20 aliphatic, and C3-20 cycloaliphatic, and three or more substituents of formula (1) wherein at least two substituents of formula (1) are attached to the aromatic core; provided that no substituents of formula (1) are in an ortho position to each other on the same aromatic ring of the core; a polymer; and one or more solvents, wherein the total solvent content is from 50 to 99 wt % based on the coating composition.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: March 26, 2024
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Sheng Liu, James F. Cameron, Shintaro Yamada, Iou-Sheng Ke, Keren Zhang, Suzanne M. Coley, Li Cui, Paul J. LaBeaume, Deyan Wang
  • Patent number: 11943877
    Abstract: A circuit board structure includes a circuit substrate having opposing first and second sides, a redistribution structure disposed at the first side, and a dielectric structure disposed at the second side. The circuit substrate includes a first circuit layer disposed at the first side and a second circuit layer disposed at the second side. The redistribution structure is electrically coupled to the circuit substrate and includes a first leveling dielectric layer covering the first circuit layer, a first thin-film dielectric layer disposed on the first leveling dielectric layer and having a material different from the first leveling dielectric layer, and a first redistributive layer disposed on the first thin-film dielectric layer and penetrating through the first thin-film dielectric layer and the first leveling dielectric layer to be in contact with the first circuit layer. The dielectric structure includes a second leveling dielectric layer disposed below the second circuit layer.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: March 26, 2024
    Assignee: Unimicron Technology Corp.
    Inventors: Wen-Yu Lin, Kai-Ming Yang, Chen-Hao Lin, Pu-Ju Lin, Cheng-Ta Ko, Chin-Sheng Wang, Guang-Hwa Ma, Tzyy-Jang Tseng
  • Publication number: 20240096630
    Abstract: Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.
    Type: Application
    Filed: January 12, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Yu-Shih Wang, Jih-Sheng Yang, Shih-Chieh Chao, Yih-Ann Lin, Ryan Chia-Jen Chen
  • Publication number: 20240097265
    Abstract: A constraining apparatus and a constraining device are described. The constraining apparatus includes a base, a positioning assembly, and a cushion assembly. The positioning assembly includes a plurality of positioning members arranged in sequence and located between two end plate assemblies. The cushion assembly is disposed on at least one of two sides of the positioning member that are opposite each other in the first direction. The constraining apparatus includes a first state and a second state, where in the first state, adjacent two of the positioning members abut against each other, such that an accommodating space for accommodating a battery cell is formed between the adjacent two of the positioning members, and the cushion assembly is configured to abut against the battery cell and the positioning members. In the second state, the plurality of positioning members are spaced apart from each other in the first direction.
    Type: Application
    Filed: March 30, 2023
    Publication date: March 21, 2024
    Applicant: CONTEMPORARY AMPEREX TECHNOLOGY CO., LIMITED
    Inventors: Jiayi ZHAO, Fangyu HUANG, Zhiguo ZHANG, Sheng TANG, Zhihui WANG
  • Publication number: 20240091569
    Abstract: Methods, apparatuses, systems, and/or the like are provided. An example method may include installing one or more filter cartridges in a blower device. An example blower device may include a housing defining at least one air inlet. An example filter cartridge may include a first filter cartridge defining a first outlet opening. The first filter cartridge may be configured to slidably engage the blower device to align the first outlet opening with at least a first portion of the at least one air inlet of the blower device in a first installed position. The one or more filter cartridges my include a second filter cartridge. The second filter cartridge may include a second outlet opening. The example method may include aligning the first outlet opening of the first filter cartridge with at least the first portion of the at least one air inlet of the blower device.
    Type: Application
    Filed: September 13, 2023
    Publication date: March 21, 2024
    Inventors: Siwei WANG, Xiaojin HAN, Hongbing XIANG, Sheng ZHOU, Anker CHEN
  • Publication number: 20240095232
    Abstract: A process of fulfilling a database deployment request for a data platform. A compute service manager of the data platform scans one or more accounts of a consumer region of the data platform for a pending listing fulfillment request, where the pending listing request includes a request for deployment of a consumer database and an associated share of grant metadata of the consumer database within the consumer region. When the compute service manager determines that an account of the one or more accounts has a pending listing fulfillment request, the compute service manager determines a listing for the pending listing fulfillment request based on listing data of the account. The compute service manager determines that no other fulfillment task is scheduled for the pending listing fulfillment request and schedules a background fulfillment task to perform the fulfillment process for the pending listing fulfillment request.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Durga Mahesh Arikatla, Laxman Mamidi, Subramanian Muralidhar, Chieh-Sheng Wang, Di Wu
  • Patent number: 11932927
    Abstract: An iron-based metal powder for ultra-high-speed laser cladding comprising chemical composition and mass percentage of the metal powder of: C 0.6˜1.0%, Cr 17.0˜20.0%, Ni 5.0˜6.5%, Mn 2.0˜4.0%, Mo 1.0˜1.5%, Ti 4.0˜6.0%, B 1.0˜1.5%, N 0.08˜0.15%, Si?0.5%, P?0.030%, S?0.030%, balance of Fe and unavoidable impurities, wherein the particle size of the metal powder is 15˜65 ?m, the fluidity is 16˜20 s/50 g.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: March 19, 2024
    Assignee: CHINA MACHINERY INSTITUTE OF ADVANCED MATERIALS (ZHENGZHOU) CO., LTD.
    Inventors: Miaohui Wang, Xueyuan Ge, Borui Du, Bowen Shen, Yifei Xu, Ning Xiao, Sheng Hao
  • Patent number: 11936844
    Abstract: An electronic device may include a lenticular display. The lenticular display may have a lenticular lens film formed over an array of pixels. The display may have a number of independently controllable viewing zones. Each viewing zone displays a respective two-dimensional image. Each eye of the viewer may receive a different one of the two-dimensional images, resulting in a perceived three-dimensional image. The electronic device may include display pipeline circuitry that generates and processes content to be displayed on the lenticular display. Content generating circuitry may initially generate content that includes a plurality of two-dimensional images, each two-dimensional image corresponding to a respective viewing zone. Pre-processing circuitry may subsequently anisotropically resize each two-dimensional image. Pixel mapping circuitry may then be used to map the resized two-dimensional images to the array of pixels in the lenticular display.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: March 19, 2024
    Assignee: Apple Inc.
    Inventors: Sheng Zhang, Chaohao Wang, Yue Ma
  • Patent number: 11932062
    Abstract: A tire surface managing method, comprising: emitting detecting light to a target object on a surface of a tire; receiving reflected detecting light from the target object and from the surface adjacent to the target object; determining whether the target object protrudes according to a distance calculated according to the reflected detecting light from the target object and a distance calculated according to the reflected detecting light from the surface; determining whether the target object forms a hole on the surface according to the distance calculated according to the reflected detecting light from the target object and the distance calculated according to the reflected detecting light from the surface; receiving the reflected detecting light from the surface to calculate a width of the hole on the tire; and activating a protection mechanism for a vehicle comprising the tire if the width is larger than a width threshold.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: March 19, 2024
    Assignee: PixArt Imaging Inc.
    Inventors: Guo-Zhen Wang, Chang-Sheng Chiu
  • Publication number: 20240087960
    Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 14, 2024
    Inventors: Yu-Lien HUANG, Ching-Feng FU, Huan-Just LIN, Fu-Sheng LI, Tsai-Jung HO, Bor Chiuan HSIEH, Guan-Xuan CHEN, Guan-Ren WANG
  • Publication number: 20240088095
    Abstract: A method for forming a chip package structure. The method includes bonding first connectors over a front surface of a semiconductor wafer. The method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. The method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 14, 2024
    Inventors: Chin-Hua WANG, Shin-Puu JENG, Po-Yao LIN, Po-Chen LAI, Shu-Shen YEH, Ming-Chih YEW, Yu-Sheng LIN
  • Publication number: 20240086362
    Abstract: A key-value store and a file system are integrated together to provide improved operations. The key-value store can include a log engine, a hash engine, a sorting engine, and a garbage collection manager. The features of the key-value store can be configured to reduce the number of I/O operations involving the file system, thereby improving read efficiency, reducing write latency, and reducing write amplification issues inherent in the combined key-value store and file system.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 14, 2024
    Inventors: Hao Wang, Jiaxin Ou, Sheng Qiu, Yi Wang, Zhengyu Yang, Yizheng Jiao, Jingwei Zhang, Jianyang Hu, Yang Liu, Ming Zhao, Hui Zhang, Kuankuan Guo, Huan Sun, Yinlin Zhang
  • Publication number: 20240087974
    Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Lin, Chin-Hua Wang, Shu-Shen Yeh, Chien-Hung Chen, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20240088063
    Abstract: A semiconductor package provided herein includes a wiring substrate, a semiconductor component, conductor terminals, a bottom stiffener and a top stiffener. The wiring substrate has a first surface and a second surface opposite to the first surface. The semiconductor component is disposed on the first surface of the wiring substrate. The conductor terminals are disposed on the second surface of the wiring substrate and electrically connected to the semiconductor component through the wiring substrate. The bottom stiffener is disposed on the second surface of the wiring substrate and positioned between the conductor terminals. The top stiffener is disposed on the first surface of the wiring substrate. The top stiffener is laterally spaced further away from the semiconductor component than the bottom stiffener.
    Type: Application
    Filed: November 23, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Hua Wang, Shu-Shen Yeh, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng