Abstract: A display substrate, a display apparatus and a manufacturing method are provided. The display substrate includes: a base substrate; a first electrode layer on a side of the base substrate; a light-emitting layer on a side of the first electrode layer facing away from the base substrate including a plurality of light-emitting portions; a second electrode layer on a side of the light-emitting layer facing away from the first electrode layer; a first transparent inhibitor layer including a plurality of mutually separated first pattern portions; and an auxiliary electrode layer including an auxiliary electrode pattern formed by inhibition of the first pattern portions, where at least part of an orthographic projection of the auxiliary electrode pattern on the base substrate is separated from orthographic projections of the first pattern portions on the base substrate, and the auxiliary electrode pattern is in contact and electrically connected with the second electrode layer.

Abstract: Embodiments of this application disclose an artificial intelligence-based (AI-based) animation character control method. When one animation character has a corresponding face customization base, and one animation character has no corresponding face customization base, the animation character having the face customization base may be used as a driving character, and the animation character having no face customization base may be used as a driven character.

Abstract: An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.

Abstract: A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to VSS and forms a ground plane. A second portion of the first conductive layer is electrically connected to VDD and forms a power plane. The first conductive layer, insulating layer, and second conductive layer constitute a decoupling capacitor. A microstrip line including a trace of the second conductive layer is formed over the insulating layer and first conductive layer. The first conductive layer is provided on an embedded dummy die, interconnect unit, or modular PCB unit.

Abstract: Disclosed are methods of producing single cut precursor microRNA (pre-miRNA) in a host cell from a primary microRNA (pri-miRNA). Also disclosed are method of increasing production levels of single cut precursor microRNA (pre-miRNA) and decreasing production levels of double cut precursor microRNA (pre-miRNA) in a host cell from a primary microRNA (pri-miRNA); a method of decreasing production levels of single cut precursor microRNA (pre-miRNA) and increasing production of double cut precursor microRNA (pre-miRNA) in a host cell from a primary microRNA (pri-miRNA); a method of modulating expression levels of microRNA (miRNA) in a host cell; a method of modulating expression levels of microRNA (miRNA) in a subject; a method of treating a disease in a subject. Also disclosed herein is a genetically modified primary microRNA (pri-miRNA).

Abstract: A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to VSS and forms a ground plane. A second portion of the first conductive layer is electrically connected to VDD and forms a power plane. The first conductive layer, insulating layer, and second conductive layer constitute a decoupling capacitor. A microstrip line including a trace of the second conductive layer is formed over the insulating layer and first conductive layer. The first conductive layer is provided on an embedded dummy die, interconnect unit, or modular PCB unit.

Abstract: A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to VSS and forms a ground plane. A second portion of the first conductive layer is electrically connected to VDD and forms a power plane. The first conductive layer, insulating layer, and second conductive layer constitute a decoupling capacitor. A microstrip line including a trace of the second conductive layer is formed over the insulating layer and first conductive layer. The first conductive layer is provided on an embedded dummy die, interconnect unit, or modular PCB unit.

Abstract: Devices are often presented with displays that are selectively designed for a particular presentation type, such as virtual reality environments, head-mounted displays, and heads-up displays. However, display design choices that promote one presentation type may diminish the usability of the device for other presentation type, requiring users to utilize multiple devices with specialized displays. Instead, a display of a device may exhibit an opacity that is selectable between a substantially opaque state and a substantially transparent state, optionally with one or more semi-opaque states. An opacity controller may receive requests from the device for a requested opacity, in response to sensor and/or logical inputs, and/or to match a selected presentation type. The opacity controller may adjust the opacity of at least one region of the opacity layer to the requested opacity, and a visual presenter may present the visual output of the device with the opacity layer.

Abstract: Methods and means are provided to enhance the selective expression of transgenes under control of a fiber-selective promoter, in fiber cells, particularly cotton fiber cells by including target sites for naturally occurring microRNAs with a specific expression profile, particularly with a differential expression profile between cells leading to fibers and other cells of the fiber producing plant, into the transcribed region of genes of interest.

Abstract: A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to VSS and forms a ground plane. A second portion of the first conductive layer is electrically connected to VDD and forms a power plane. The first conductive layer, insulating layer, and second conductive layer constitute a decoupling capacitor. A microstrip line including a trace of the second conductive layer is formed over the insulating layer and first conductive layer. The first conductive layer is provided on an embedded dummy die, interconnect unit, or modular PCB unit.

Abstract: A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to VSS and forms a ground plane. A second portion of the first conductive layer is electrically connected to VDD and forms a power plane. The first conductive layer, insulating layer, and second conductive layer constitute a decoupling capacitor. A microstrip line including a trace of the second conductive layer is formed over the insulating layer and first conductive layer. The first conductive layer is provided on an embedded dummy die, interconnect unit, or modular PCB unit.

Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.

Abstract: Methods and means are provided to enhance the selective expression of transgenes under control of a fiber-selective promoter, in fiber cells, particularly cotton fiber cells by including target sites for naturally occurring microRNAs with a specific expression profile, particularly with a differential expression profile between cells leading to fibers and other cells of the fiber producing plant, into the transcribed region of genes of interest.

Abstract: A bicycle derailleur includes: a passive first derailleur, installed on a fasten plate and a rear shaft of a bicycle and provided with a chain pulling arm; and characterized in that: an active second derailleur is provided, a lower fasten part thereof and a lower fasten part of the passive first derailleur and a horizontal frame rod of the bicycle are provided with a guide plate, the upper portion of the guide plate is disposed at the front end of the chain, the middle portion thereof is disposed at the lower fasten part of the active second derailleur, and the lower portion thereof is disposed on a fasten shaft of the passive first derailleur. Accordingly, the active second derailleur is enabled to allow the guide plate to synchronously drive the passive first derailleur and the shifting is able to be achieved through the chain being normally or reversely operated.

Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.

Abstract: A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to VSS and forms a ground plane. A second portion of the first conductive layer is electrically connected to VDD and forms a power plane. The first conductive layer, insulating layer, and second conductive layer constitute a decoupling capacitor. A microstrip line including a trace of the second conductive layer is formed over the insulating layer and first conductive layer. The first conductive layer is provided on an embedded dummy die, interconnect unit, or modular PCB unit.

Abstract: The invention provides nine oligonuleotides with sequences of SEQ ID NO:1-9 or their functional homologues or a composition comprising the same and a method for treating B cell neoplasm by using the oligonuleotides or their functional homologues or the composition comprising the oligonuleotides. The oligonuleotides induce the apoptosis of B cell neoplastic cells, up-regulate CD40 on B cell neoplastic cells and stimulate the production of IL-10 from B cell neoplastic cells.

Abstract: The invention provides nine oligonuleotides with sequences of SEQ ID NO:1-9 or their functional homologues or a composition comprising the same and a method for treating B cell neoplasm by using the oligonuleotides or their functional homologues or the composition comprising the oligonuleotides. The oligonuleotides induce the apoptosis of B cell neoplastic cells, up-regulate CD40 on B cell neoplastic cells and stimulate the production of IL-10 from B cell neoplastic cells.

Abstract: The invention provides an oligonucleotide with a sequence of SEQ ID NO: 1 or its functional homolgue, a composition comprising the same and a method for treating B cell neoplasm by using the oligonucleotide or its functional homologue or the composition comprising the oligonucleotide. The oligonulceotide induces the apoptosis of B cell neoplastic cells, up-regulates CD40 on B cell neoplastic cells and stimulates the production of IL-10 from B cell neoplastic cells.

Abstract: A flip chip style semiconductor package has a substrate with a plurality of active devices formed thereon. A contact pad is formed over the substrate. An under bump metallization (UBM) layer is in electrical contact with the contact pad. A passivation layer is formed over the substrate. In one case, the UBM layer is disposed above the passivation layer. Alternatively, the passivation layer is disposed above the UBM layer. A portion of the passivation layer is removed to create a passivation island. The passivation island is centered with respect to the contact pad with its top surface devoid of the UBM layer. A solder bump is formed over the passivation island in electrical contact with the UBM layer. The passivation island forms a void in the solder bump for stress relief. The UBM layer may include a redistribution layer such that the passivation island is offset from the contact pad.