Patents by Inventor Sheng-Chang Chen
Sheng-Chang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966133Abstract: An electronic device is disclosed. The electronic device includes a substrate, a plurality of color filters disposed on the substrate, an optical film disposed on the plurality of color filter, and a defect disposed between the substrate and the optical film. The optical film has a first base, a protective layer on the first base, and a second base between the first base and the protective layer and having a first processed area. In a top view of the electronic device, the first processed area corresponds to the defect and at least partially overlaps at least two color filters.Type: GrantFiled: May 18, 2023Date of Patent: April 23, 2024Assignee: INNOLUX CORPORATIONInventors: Tai-Chi Pan, Chin-Lung Ting, I-Chang Liang, Chih-Chiang Chang Chien, Po-Wen Lin, Kuang-Ming Fan, Sheng-Nan Chen
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Publication number: 20240096803Abstract: An integrated circuit includes a device, a first interconnect structure disposed above the device and a second interconnect structure positioned below the device. The first interconnect structure includes multiple frontside metal layers. The second interconnect structure includes multiple backside metal layers, where each backside metal layer includes metal conductors routed according to diagonal routing. In some embodiments, a backside interconnect structure can include another backside metal layer that includes metal conductors routed according to mixed-Manhattan-diagonal routing. A variety of techniques can be used to route signals between metal conductors in the backside interconnect structure and cells on one or more frontside metal layers.Type: ApplicationFiled: November 22, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Hsiung Chen, Jerry Chang Jui Kao, Kuo-Nan Yang, Jack Liu
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Publication number: 20240077534Abstract: Systems, methods, and devices are described herein for pre-setting scan flip-flops using combinational logic circuits. A system includes a plurality of flip-flop devices and a first pre-setting combinational logic circuit. The plurality of flip-flop devices are coupled together in series and configured to receive a scan input signal, capture data output from each flip-flop device of the plurality of flip-flop devices based on the scan input signal, and generate a scan output signal comprising the captured data. The first pre-setting combinational logic circuit is coupled to a first flip-flop device of the plurality of flip-flop devices. The first pre-setting combinational logic circuit includes a plurality of transistors and is configured to override and set either the scan input signal to the first flip-flop device or the scan output signal of the first flip-flop device based on selective operation of the plurality of transistors.Type: ApplicationFiled: January 6, 2023Publication date: March 7, 2024Inventors: Johnny Chiahao Li, Sheng-Hsiung Chen, Tzu-Ying Lin, Yung-Chen Chien, Jerry Chang Jui Kao, Xiangdong Chen
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Publication number: 20240070364Abstract: An integrated circuit includes a first power rail and a second power rail extending in a first direction, and a first power grid stub connected to the first power rail through a first via-connector. The integrated circuit also includes a first vertical conducting line extending in a second direction in a circuit cell between a first vertical cell boundary and a second vertical cell boundary. The first vertical conducting line and the first power grid stub are in a same metal layer and aligned with each other along the second direction.Type: ApplicationFiled: August 23, 2022Publication date: February 29, 2024Inventors: Johnny Chiahao LI, Sheng-Hsiung CHEN, Hui-Zhong ZHUANG, Jerry Chang Jui KAO, Xiangdong CHEN, Chung-Hsing WANG
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Publication number: 20240069299Abstract: An optical element driving mechanism includes a movable assembly, a fixed assembly, and a driving assembly. The movable assembly is configured to be connected to an optical element. The movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly in a range of motion. The optical element driving mechanism further includes a positioning assembly configured to position the movable assembly at a predetermined position relative to the fixed assembly when the driving assembly is not operating.Type: ApplicationFiled: November 9, 2023Publication date: February 29, 2024Inventors: Chao-Chang HU, Kuen-Wang TSAI, Liang-Ting HO, Chao-Hsi WANG, Chih-Wei WENG, He-Ling CHANG, Che-Wei CHANG, Sheng-Zong CHEN, Ko-Lun CHAO, Min-Hsiu TSAI, Shu-Shan CHEN, Jungsuck RYOO, Mao-Kuo HSU, Guan-Yu SU
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Patent number: 11910619Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory device. The method includes forming a first memory cell and a second memory cell over a substrate. A first dielectric layer is formed over and around the first and second memory cells. The first dielectric layer comprises sidewalls defining an opening spaced laterally between the first and second memory cells. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is disposed in the opening. A planarization process is performed on the first and second dielectric layers. At least a portion of the second dielectric layer is in the opening after the planarization process.Type: GrantFiled: March 24, 2022Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Chang Chen, Sheng-Huang Huang
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Publication number: 20230389446Abstract: The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation the same. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. Two protection layers sequentially surround a sidewall of the MTJ. The two protection layers have etch selectivity over one another.Type: ApplicationFiled: August 8, 2023Publication date: November 30, 2023Inventors: Sheng-Chang CHEN, Harry-Hak-Lay CHUANG, Hung Cho WANG, Sheng-Huang HUANG
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Publication number: 20230140896Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a first memory cell and a second memory cell over a substrate, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; depositing a first dielectric layer over the first and second memory cells, such that the first dielectric layer has a void between the first and second memory cells; depositing a second dielectric layer over the first dielectric layer; and forming a first conductive feature and a second conductive feature in the first and second dielectric layers and respectively connected with the top electrode of the first memory cell and the top electrode of the second memory cell.Type: ApplicationFiled: January 9, 2023Publication date: May 11, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Harry-Hak-Lay CHUANG, Sheng-Huang HUANG, Hung-Cho WANG, Sheng-Chang CHEN
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Publication number: 20230061985Abstract: A MRAM device includes a substrate, a first bottom electrode, a first MTJ stack, a first spacer, a topography-smoothing layer and a second ILD layer. The substrate includes a first ILD layer having a metal line. The first MTJ stack is over the first bottom electrode. The first spacer surrounds sidewalls of the first MTJ stack. The topography-smoothing layer extends over a top surface of the first ILD layer, along sidewalls of the first bottom electrode the first spacer. The topography-smoothing layer has a top portion over the first MTJ stack and a first side portion laterally surrounding the first spacer. The first side portion has a maximal lateral thickness greater than a maximal vertical thickness of the top portion. The second ILD layer is over the topography-smoothing layer and has a material different from a material of the topography-smoothing layer.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Harry-Hak-Lay CHUANG, Sheng-Chang CHEN, Hung Cho WANG, Sheng-Huang HUANG
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Patent number: 11551736Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a first memory cell and a second memory cell over a substrate, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; depositing a first dielectric layer over the first and second memory cells, such that the first dielectric layer has a void between the first and second memory cells; depositing a second dielectric layer over the first dielectric layer; and forming a first conductive feature and a second conductive feature in the first and second dielectric layers and respectively connected with the top electrode of the first memory cell and the top electrode of the second memory cell.Type: GrantFiled: July 30, 2020Date of Patent: January 10, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Harry-Hak-Lay Chuang, Sheng-Huang Huang, Hung-Cho Wang, Sheng-Chang Chen
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Publication number: 20220352457Abstract: A method for manufacturing a memory device includes forming a dielectric layer over a substrate, in which the substrate has a cell region and a logic region adjacent to the cell region. A bottom electrode, a memory layer, and a top electrode are formed in sequence over the cell region of the substrate. A first spacer is formed extending upwards from the bottom electrode. A second spacer is formed extending upwards from the dielectric layer and lining with sidewalls of the bottom electrode and the first spacer.Type: ApplicationFiled: April 28, 2021Publication date: November 3, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Harry-Hak-Lay CHUANG, Hung-Cho WANG, Sheng-Chang CHEN, Jun-Yao CHEN, Chang-Jen HSIEH
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Patent number: 11469269Abstract: Some embodiments relate to an integrated chip. The integrated chip includes a first memory cell overlying a substrate and a second memory cell overlying the substrate. A dielectric structure overlies the substrate. A trench extends into the dielectric structure and is spaced laterally between the first memory cell and the second memory cell. A dielectric layer is disposed within the trench.Type: GrantFiled: July 16, 2020Date of Patent: October 11, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chang Chen, Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Huang Huang
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Publication number: 20220319920Abstract: The present disclosure relates to an integrated chip in some embodiments. The integrated chip includes a memory device disposed over a lower interconnect within one or more lower inter-level dielectric (ILD) layers over a substrate. An upper ILD layer laterally surrounds the memory device. An etch stop layer is disposed along a sidewall of the memory device and over an upper surface of the one or more lower ILD layers. An upper interconnect is arranged along opposing sides of the memory device. The upper interconnect rests of an upper surface of the etch stop layer. The upper surface of the etch stop layer is vertically below a top of the memory device.Type: ApplicationFiled: June 17, 2022Publication date: October 6, 2022Inventors: Sheng-Huang Huang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Chang Chen
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Patent number: 11437433Abstract: Some embodiments relate to a method for forming a memory device. The method includes forming a first memory cell over a substrate and forming a second memory cell over the substrate. Further, an inter-level dielectric (ILD) layer is formed over the substrate such that the ILD layer comprises sidewalls defining a first trough between the first memory cell and the second memory cell. In addition, a first dielectric layer is formed over the ILD layer and within the first trough.Type: GrantFiled: July 16, 2020Date of Patent: September 6, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chang Chen, Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Huang Huang
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Publication number: 20220246843Abstract: Some embodiments relate to a semiconductor structure having a magnetic tunnel junction (MTJ) on a substrate and a top electrode on the MTJ. A first segment of a top surface of the top electrode adjacent to a first sidewall of the top electrode is different from a second segment of the top surface of the top electrode adjacent to a second sidewall of the top electrode. A sidewall spacer comprises a first spacer on the first sidewall of the top electrode and a second spacer on the second sidewall of the top electrode. A first surface of the first spacer comprises a first curve and a second surface of the second spacer comprises a second curve. A dielectric layer is around the MTJ and top electrode.Type: ApplicationFiled: April 21, 2022Publication date: August 4, 2022Inventors: Harry-Hak-Lay Chuang, Chen-Pin Hsu, Hung Cho Wang, Wen-Chun You, Sheng-Chang Chen, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang
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Publication number: 20220216268Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory device. The method includes forming a first memory cell and a second memory cell over a substrate. A first dielectric layer is formed over and around the first and second memory cells. The first dielectric layer comprises sidewalls defining an opening spaced laterally between the first and second memory cells. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is disposed in the opening. A planarization process is performed on the first and second dielectric layers. At least a portion of the second dielectric layer is in the opening after the planarization process.Type: ApplicationFiled: March 24, 2022Publication date: July 7, 2022Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Chang Chen, Sheng-Huang Huang
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Patent number: 11380580Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming a memory device over a substrate and forming an etch stop layer over the memory device. An inter-level dielectric (ILD) layer is formed over the etch stop layer and laterally surrounding the memory device. One or more patterning process are performed to define a first trench extending from a top of the ILD layer to expose an upper surface of the etch stop layer. A removal process is performed to remove an exposed part of the etch stop layer. A conductive material is formed within the interconnect trench after performing the removal process.Type: GrantFiled: August 31, 2020Date of Patent: July 5, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Huang Huang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Chang Chen
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Patent number: 11322543Abstract: Various embodiments of the present disclosure are directed towards a memory device including a protective sidewall spacer layer that laterally encloses a memory cell. An upper inter-level dielectric (ILD) layer overlying a substrate. The memory cell is disposed with the upper ILD layer. The memory cell includes a top electrode, a bottom electrode, and a magnetic tunnel junction (MTJ) structure disposed between the top and bottom electrodes. A sidewall spacer structure laterally surrounds the memory cell. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and the protective sidewall spacer layer. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different from the first material. A conductive wire overlying the first memory cell. The conductive wire contacts the top electrode and the protective sidewall spacer layer.Type: GrantFiled: May 27, 2020Date of Patent: May 3, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Chang Chen, Sheng-Huang Huang
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Publication number: 20220036932Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a first memory cell and a second memory cell over a substrate, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; depositing a first dielectric layer over the first and second memory cells, such that the first dielectric layer has a void between the first and second memory cells; depositing a second dielectric layer over the first dielectric layer; and forming a first conductive feature and a second conductive feature in the first and second dielectric layers and respectively connected with the top electrode of the first memory cell and the top electrode of the second memory cell.Type: ApplicationFiled: July 30, 2020Publication date: February 3, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Harry-Hak-Lay CHUANG, Sheng-Huang HUANG, Hung-Cho WANG, Sheng-Chang CHEN
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Publication number: 20210375987Abstract: Various embodiments of the present disclosure are directed towards a memory device including a protective sidewall spacer layer that laterally encloses a memory cell. An upper inter-level dielectric (ILD) layer overlying a substrate. The memory cell is disposed with the upper ILD layer. The memory cell includes a top electrode, a bottom electrode, and a magnetic tunnel junction (MTJ) structure disposed between the top and bottom electrodes. A sidewall spacer structure laterally surrounds the memory cell. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and the protective sidewall spacer layer. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different from the first material. A conductive wire overlying the first memory cell. The conductive wire contacts the top electrode and the protective sidewall spacer layer.Type: ApplicationFiled: May 27, 2020Publication date: December 2, 2021Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Chang Chen, Sheng-Huang Huang