Abstract: A bottom gate thin film transistor and an active array substrate are provided. The bottom gate thin film transistor includes a gate, a gate insulation layer, a semiconductor layer, a plurality of sources and a plurality of drains. The gate insulation layer is disposed on the gate. The semiconductor layer is disposed on the gate insulation layer and located above the gate. An area ratio of the semiconductor layer and the gate is about 0.001 to 0.9. The sources are electrically connected with each other, and the drains are electrically connected with each other.

Abstract: A bidirectional shift register includes first, second, third and four control signal bus lines for providing first, second, third and fourth control signals, Bi1, Bi2, Bi3 and Bi4, respectively, and a plurality of shift register stages electrically coupled in serial, each shift register stage having a first input node and a second input node, where the plurality of shift register stages is grouped into a first section and a second section, wherein the first and second input nodes of each shift register stage in the first section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi1 and Bi2, respectively, and the first and second input nodes of each shift register stage in the second section are electrically coupled to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3 and Bi4, respectively.

Abstract: The present invention relates to a shift register having a plurality of stages electrically coupled to each other in series. Each stage includes a first and second TFT transistor. The first TFT transistor has a get electrically coupled to the output of the immediately prior stage, a drain electrically coupled to the boost point of the stage, and a source configured to receive one of the first and second control signals. The second TFT transistor has a get electrically coupled to the output of the immediately next stage, a drain and a source electrically coupled the drain and the source of the first transistor, respectively.

Abstract: An exemplary driving method is adapted for a bistable display device including a pixel array. The pixel array includes a plurality of first pixels and a plurality of second pixels arranged in a predetermined manner. The driving method includes the following steps of: during a first time period, providing the first pixels with a first pixel voltage for black insertion and providing the second pixels with a second pixel voltage different from the first pixel voltage; during a second time period following the first time period, providing the first pixels with the second pixel voltage for white insertion and maintaining the second pixels provided with the second pixel voltage for white insertion; and during a third time period following the second time period, initiating the first pixels to display a gray scale image and providing the second pixels with the first pixel voltage for black insertion.

Abstract: The present invention relates to a shift register having a plurality of stages electrically coupled to each other in series. Each stage includes a first and second TFT transistor. The first TFT transistor has a get electrically coupled to the output of the immediately prior stage, a drain electrically coupled to the boost point of the stage, and a source configured to receive one of the first and second control signals. The second TFT transistor has a get electrically coupled to the output of the immediately next stage, a drain and a source electrically coupled the drain and the source of the first transistor, respectively.

Abstract: A bidirectional shift register includes first, second, third and four control signal bus lines for providing first, second, third and fourth control signals, Bi1, Bi2, Bi3 and Bi4, respectively, and a plurality of shift register stages electrically coupled in serial, each shift register stage having a first input node and a second input node, where the plurality of shift register stages is grouped into a first section and a second section, wherein the first and second input nodes of each shift register stage in the first section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi1 and Bi2, respectively, and the first and second input nodes of each shift register stage in the second section are electrically coupled to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3 and Bi4, respectively.

Abstract: A pixel array which comprises a display area, a plurality of scan lines and a plurality of drivers is provided. The display area has a first side, a second side in opposition to the first side and a plurality of pixels. The scan lines are electrically connected to the pixels, respectively. The drivers are electrically connected to the scan lines, respectively. The pixels are arranged along the first direction in sequence. The drivers are located on the first side and the second side of the display area, and are arranged along the second direction in sequence. The first direction is orthogonal to the second direction.

Abstract: A flat panel display with a circuit protection structure is provided. The flat panel display includes a substrate, an electrode array control circuit, a driving circuit, a display panel, and a protection unit. The substrate has a first surface. The electrode array control circuit is formed on the first surface. The driving circuit is formed on the first surface and on one side of the electrode array control circuit. The display panel including a plurality of display particles is disposed on the electrode array control circuit. The electrode array control circuit controls operations of the display particles. The protection unit is formed on one side of the display panel to cover the driving circuit.

Abstract: A display device includes a substrate, a plurality of first signal lines, a plurality of second signal lines, and a plurality of first signal internal links. The first signal lines and the second signal lines are crossed and disposed in a display region of the substrate. The first signal internal links are disposed in the display region of the substrate, wherein each of the first signal internal links is electrically connected to a corresponding first signal line and disposed between two adjacent second signal lines. Each of the first signal internal links intersects the first signal lines, and the number of intersection points of each of the first signal internal links and the first signal lines is the same.

Abstract: A bidirectional controlling device is utilized for receiving two input signals, which are respectively provided from a first input terminal and a second input terminal, and for respectively providing two output signals to a first output terminal and a second output terminal, by controlling a plurality of switch sets.

Abstract: A display device includes a substrate, gate lines, data lines, data signal links, and contact vias. The substrate includes a display region, and a peripheral region surrounding the display region. The gate lines, data lines, data signal links, and contact vias are disposed within the display region of the substrate. The gate lines cross the data lines. Each of the data signal links is disposed between adjacent gate lines. Each of the contact vias is disposed between each of the data signal links and a corresponding data line, such that each of the data signal links is electrically connected with the corresponding data line.

Abstract: A liquid crystal display panel includes a sub-pixel array, a plurality of scan lines, and a plurality of data lines. The sub-pixel array has a plurality of sub-pixels arranged in array. Any two neighboring scan lines of the scan lines and a row of the sub-pixels disposed between the two neighboring scan liens are electrically connected. The sub-pixels arranged in odd rows are electrically connected to the odd-numbered data lines, and the sub-pixels arranged in even rows are electrically connected to the even-numbered data lines. Thus, the liquid crystal display panel is able to reduce mura phenomenon through the above-mentioned layout. A driving method of the above-mentioned liquid crystal display panel is also provided.

Abstract: A bottom gate thin film transistor and an active array substrate are provided. The bottom gate thin film transistor includes a gate, a gate insulation layer, a semiconductor layer, a plurality of sources and a plurality of drains. The gate insulation layer is disposed on the gate. The semiconductor layer is disposed on the gate insulation layer and located above the gate. An area ratio of the semiconductor layer and the gate is about 0.001 to 0.9. The sources are electrically connected with each other, and the drains are electrically connected with each other.

Abstract: A liquid crystal display (LCD) is provided. The LCD includes a display panel and a voltage supply device (VSD). The display panel includes a plurality of scan lines, a plurality of data lines disposed substantially perpendicularly with the scan lines, and a plurality of pixels. The pixels are respectively electrically connected with the corresponding data line and the corresponding scan line, and are arranged in an array. Each of the pixels includes a common line and a compensation line, wherein the common line is located in the transparent area to receive a common voltage, and the compensation line is located in the reflection area to receive a stable voltage. The VSD is coupled to the compensation line of each of the pixels for continuously and correspondingly providing the stable voltage to the compensation line of each of the pixels.

Abstract: A high-reliability gate driving circuit includes a plurality of odd shift register stages and a plurality of even shift register stages. Each odd shift register stage generates a corresponding gate signal furnished to a corresponding odd gate line according to a first clock and a second clock having a phase opposite to the first clock, and further functions to pull down a gate signal of at least one even gate line or at least one odd gate line different from the corresponding odd gate line. Each even shift register stage generates a corresponding gate signal furnished to a corresponding even gate line according to a third clock and a fourth clock having a phase opposite to the third clock, and further functions to pull down a gate signal of at least one odd gate line or at least one even gate line different from the corresponding even gate line.

Abstract: An LCD device includes a plurality of data lines, a plurality gate lines, a pixel matrix, and a source driver. The pixel matrix includes an mth pixel column and an (m+1)th pixel column. The odd-numbered pixels of the mth pixel column are coupled to an mth data line and corresponding odd-numbered gate lines. The even-numbered pixels of the mth pixel column is coupled to an (m+1)th data line and corresponding even-numbered gate lines. The odd-numbered pixels of the (m+1)th pixel column is coupled to the (m+1)th data line and corresponding odd-numbered gate lines. The even-numbered pixels of the (m+1)th pixel column is coupled to an (m+2)th data line and corresponding even-numbered gate lines. The gate driver outputs the data driving signals having a first polarity to the odd-numbered data lines, and outputs the data driving signals having a second polarity to the even-numbered data lines.

Abstract: The present invention relates to a shift register having a plurality of stages electrically coupled to each other in series. Each stage includes a first and second TFT transistor. The first TFT transistor has a get electrically coupled to the output of the immediately prior stage, a drain electrically coupled to the boost point of the stage, and a source configured to receive one of the first and second control signals. The second TFT transistor has a get electrically coupled to the output of the immediately next stage, a drain and a source electrically coupled the drain and the source of the first transistor, respectively.

Abstract: A single clock driven shift register comprising multiple stages is provided. The (M)th stage comprises a latch unit, a logic unit, and a non-overlap buffer. The latch unit latches an input signal from the (M?1)th stage according to a clock signal. The logic unit connecting to an output terminal of the latch unit deals with an output signal of the latch unit and the clock signal with an NAND logic calculation. The non-overlap buffer connecting to the output terminal of the logic unit comprises at least three inverters connected in a serial, and an output signal of the first inverter coupled to the output terminal of the logic unit is input to an latch unit of the (M+1)th stage. Meanwhile, an output signal of the non-overlap buffer of the (M?1)th stage is input to the non-overlap buffer or the logic unit to delay the output signal of the non-overlap buffer.

Abstract: A shift register comprises a plurality of stages, {Sj}, j=1, 2, . . . , N, N being a positive integer.

Abstract: A tri-gate pixel structure includes three sub-pixel regions, three gate lines, a data line, three thin film transistors (TFTs), three pixel electrodes, and a common line. The gate lines are disposed along a first direction, and the data line is disposed along a second direction. The TFTs are disposed in the sub-pixel regions respectively, wherein each TFT has a gate electrode electrically connected to a corresponding gate line, a source electrode electrically connected to the data line, and a drain electrode. The three pixel electrodes are disposed in the three sub-pixel regions respectively, and each pixel electrode is electrically connected to the drain electrode of one TFT respectively. The common line crosses the gate lines and partially overlaps the three gate lines, and the common line and the three pixel electrodes are partially overlapped to respectively form three storage capacitors.