Abstract: A liquid crystal display device includes a gate driver for generating a first scan signal voltage and a second scan signal voltage, a source driver for generating a first polarity data voltage and a second polarity data voltage, and a liquid crystal display panel having a first pixel set and a second pixel set. Each first and second pixel set includes a first pixel and a second pixel. Both the first pixel of the first pixel set and the second pixel of the second pixel set display grey level based on the first polarity data voltage in response to the first scan signal voltage. Both the second pixel of the first pixel set and the first pixel of the second pixel set display grey level based on the second polarity data voltage in response to the second scan signal voltage.

Abstract: A bidirectional controlling device is utilized for receiving two input signals, which are respectively provided from a first input terminal and a second input terminal, and for respectively providing two output signals to a first output terminal and a second output terminal, by controlling a plurality of switch sets.

Abstract: A discharging device is used to reduce the voltage level at a bootstrap point in an electronic circuit such as a shift register circuit. In such a circuit, a first transistor in a conducting state receives an input pulse and conveys it to the gate terminal of a second transistor, causing the second transistor to be in a conducting state. This gate terminal is known as a bootstrap point. After receiving the input pulse, an output pulse is produced at one drain/source terminal of the second transistor. During the time period of the output pulse, the first transistor is in a non-conducting state and the voltage level at the bootstrap point is high, imposing a stress upon the first transistor. A discharging circuit consisting of at least one transistor is coupled to the bootstrap point in order to reduce the voltage level at the output pulse period.

Abstract: Pixel structures and methods for fabricating the same are provided. The pixel structure comprises a thin film transistor formed on a substrate. The thin film transistor comprises a gate electrode and an active layer. The active layer comprises a source region and a drain region doped with a first dopant. A capacitor is formed on the substrate. The capacitor comprises a lower electrode and an upper electrode. The lower electrode is doped with a second dopant electrically connecting the source region. The first dopant and the second dopant are of different types.

Abstract: A single clock driven shift register comprising multiple stages is provided. The (M)th stage comprises a latch unit, a logic unit, and a non-overlap buffer. The latch unit latches an input signal from the (M?1)th stage according to a clock signal. The logic unit connecting to an output terminal of the latch unit deals with an output signal of the latch unit and the clock signal with an NAND logic calculation. The non-overlap buffer connecting to the output terminal of the logic unit comprises at least three inverters connected in a serial, and an output signal of the first inverter coupled to the output terminal of the logic unit is input to an latch unit of the (M+1)th stage. Meanwhile, an output signal of the non-overlap buffer of the (M?1)th stage is input to the non-overlap buffer or the logic unit to delay the output signal of the non-overlap buffer.