Abstract: A complementary metal-oxide-semiconductor (CMOS) image sensor having a passivation layer is provided. The CMOS image sensor includes a sensing device substrate. Isolation structures are positioned within trenches of the sensing device substrate. The isolation structures are arranged along opposing sides of a plurality of image sensing devices. The CMOS image sensor also includes a passivation layer. The passivation layer includes passivation sidewalls arranged along the sidewalls of the isolation structures. A metallic grid overlies the passivation layer. The metallic grid includes a metal framework surrounding openings overlying the plurality of image sensing devices. The passivation layer further includes passivation section underlying the openings.

Abstract: A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the device die is patterned to extend the opening further into the device die. After patterning, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material.

Abstract: An apparatus for and a method of bonding a first substrate and a second substrate are provided. In an embodiment a first wafer chuck has a first curved surface and a second wafer chuck has a second curved surface. A first wafer is placed on the first wafer chuck and a second wafer is placed on a second wafer chuck, such that both the first wafer and the second wafer are pre-warped prior to bonding. Once the first wafer and the second wafer have been pre-warped, the first wafer and the second wafer are bonded together.

Abstract: Methods for improving hybrid bond yield for semiconductor wafers forming 3DIC devices includes first and second wafers having dummy and main metal deposited and patterned during BEOL processing. Metal of the dummy metal pattern occupies from about 40% to about 90% of the surface area of any given dummy metal pattern region. High dummy metal surface coverage, in conjunction with utilization of slotted conductive pads, allows for improved planarization of wafer surfaces presented for hybrid bonding. Planarized wafers exhibit minimum topographic differentials corresponding to step height differences of less than about 400 ?. Planarized first and second wafers are aligned and subsequently hybrid bonded with application of heat and pressure; dielectric-to-dielectric, RDL-to-RDL. Lithography controls to realize WEE from about 0.5 mm to about 1.5 mm may be employed to promote topographic uniformity at wafer edges.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.

Abstract: In some embodiments, the present disclosure relates to a multi-dimensional integrated chip having a redistribution structure vertically extending between integrated chip die at a location laterally offset from a bond pad. The integrated chip structure has a first die and a second die. The first die has a first plurality of interconnect layers arranged within a first dielectric structure disposed on a first substrate. The second die has a second plurality of interconnect layers arranged within a second dielectric structure disposed between the first dielectric structure and a second substrate. A bond pad is disposed within a recess extending through the second substrate. A redistribution structure electrically couples the first die to the second die at a position that is laterally offset from the bond pad.

Abstract: A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.

Abstract: Some embodiments of the present disclosure relate to a method in which a functional layer is formed over an upper semiconductor surface of a semiconductor substrate, and a capping layer is formed over the functional layer. A first etchant is used to form a recess through the capping layer and through the functional layer. The recess has a first depth and exposes a portion of the semiconductor substrate there through. A protective layer is formed along a lower surface and inner sidewalls of the recess. A second etchant is used to remove the protective layer from the lower surface of the recess and to extend the recess below the upper semiconductor surface to a second depth to form a deep trench. To prevent etching of the functional layer, the protective layer remains in place along the inner sidewalls of the recess while the second etchant is used.

Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.

Abstract: The present disclosure relates to a multi-dimensional integrated chip having a redistribution layer vertically extending between integrated chip die, which is laterally offset from a back-side bond pad. The multi-dimensional integrated chip has a first integrated chip die with a first plurality of metal interconnect layers disposed within a first inter-level dielectric layer arranged onto a front-side of a first semiconductor substrate. The multi-dimensional integrated chip also has a second integrated chip die with a second plurality of metal interconnect layers disposed within a second inter-level dielectric layer abutting the first ILD layer. A bond pad is disposed within a recess extending through the second semiconductor substrate. A redistribution layer vertically extends between the first plurality of metal interconnect layers and the second plurality of metal interconnect layers at a position that is laterally offset from the bond pad.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.

Abstract: Methods for improving hybrid bond yield for semiconductor wafers forming 3DIC devices includes first and second wafers having dummy and main metal deposited and patterned during BEOL processing. Metal of the dummy metal pattern occupies from about 40% to about 90% of the surface area of any given dummy metal pattern region. High dummy metal surface coverage, in conjunction with utilization of slotted conductive pads, allows for improved planarization of wafer surfaces presented for hybrid bonding. Planarized wafers exhibit minimum topographic differentials corresponding to step height differences of less than about 400 ?. Planarized first and second wafers are aligned and subsequently hybrid bonded with application of heat and pressure; dielectric-to-dielectric, RDL-to-RDL. Lithography controls to realize WEE from about 0.5 mm to about 1.5 mm may also be employed to promote topographic uniformity at wafer edges.

Abstract: Some embodiments of the present disclosure relate to a deep trench isolation (DTI) structure configured to enhance efficiency and performance of a photovoltaic device. The photovoltaic device comprises a functional layer disposed over an upper surface of a semiconductor substrate, and a pair of pixels formed within the semiconductor substrate, which are separated by the DTI structure. The DTI structure is arranged within a deep trench. Sidewalls of the deep trench are partially covered with a protective sleeve formed along the functional layer prior to etching the deep trench. The protective sleeve prevents etching of the functional layer while etching the deep trench, which prevents contaminants from penetrating the pair of pixels. The protective sleeve also narrows the width of the DTI structure, which increases pixel area and subsequently the efficiency and performance of the photovoltaic device.

Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.

Abstract: The present disclosure relates to a multi-dimensional integrated chip having a redistribution layer vertically extending between integrated chip die, which is laterally offset from a back-side bond pad. The multi-dimensional integrated chip has a first integrated chip die with a first plurality of metal interconnect layers disposed within a first inter-level dielectric layer arranged onto a front-side of a first semiconductor substrate. The multi-dimensional integrated chip also has a second integrated chip die with a second plurality of metal interconnect layers disposed within a second inter-level dielectric layer abutting the first ILD layer. A bond pad is disposed within a recess extending through the second semiconductor substrate. A redistribution layer vertically extends between the first plurality of metal interconnect layers and the second plurality of metal interconnect layers at a position that is laterally offset from the bond pad.

Abstract: A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the device die is patterned to extend the opening further into the device die. After patterning, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material.

Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.

Abstract: A method embodiment includes patterning an opening through a layer at a surface of a device die. The method further includes forming a liner on sidewalls of the opening, patterning the device die to extend the opening further into the device die. After patterning the device die, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material.

Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.

Abstract: A vertical-gate transfer transistor of an active pixel sensor (APS) is provided. The transistor includes a semiconductor substrate, a vertical trench extending into the semiconductor substrate, a dielectric lining the vertical trench, and a vertical gate filling the lined vertical trench. The dielectric includes a dielectric constant exceeding 3.9 (i.e., the dielectric constant of silicon dioxide). A method of manufacturing the vertical-gate transfer transistor, an APS including the vertical-gate transfer transistor, a method of manufacturing the APS, and an image sensor including a plurality of the APSs are also provided.