Patents by Inventor Sheng-Chau Chen

Sheng-Chau Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170207176
    Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.
    Type: Application
    Filed: April 3, 2017
    Publication date: July 20, 2017
    Inventors: Cheng-Hsien Chou, Sheng-Chau Chen, Chun-Wei Chang, Kai-Chun Hsu, Chih-Yu Lai, Wei-Cheng Hsu, Hsiao-Hui Tseng, Shih Pei Chou, Shyh-Fann Ting, Tzu-Hsuan Hsu, Ching-Chun Wang, Yeur-Luen Tu, Dun-Nian Yaung
  • Patent number: 9704827
    Abstract: The present disclosure relates to a multi-dimensional integrated chip having a redistribution layer vertically extending between integrated chip die, which is laterally offset from a back-side bond pad. The multi-dimensional integrated chip has a first integrated chip die with a first plurality of metal interconnect layers disposed within a first inter-level dielectric layer arranged onto a front-side of a first semiconductor substrate. The multi-dimensional integrated chip also has a second integrated chip die with a second plurality of metal interconnect layers disposed within a second inter-level dielectric layer abutting the first ILD layer. A bond pad is disposed within a recess extending through the second semiconductor substrate. A redistribution layer vertically extends between the first plurality of metal interconnect layers and the second plurality of metal interconnect layers at a position that is laterally offset from the bond pad.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: July 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sin-Yao Huang, Chun-Chieh Chuang, Ching-Chun Wang, Sheng-Chau Chen, Dun-Nian Yaung, Feng-Chi Hung, Yung-Lung Lin
  • Publication number: 20170194273
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.
    Type: Application
    Filed: May 17, 2016
    Publication date: July 6, 2017
    Inventors: SHENG-CHAU CHEN, SHIH-PEI CHOU, MING-JHE LEE, KUO-MING WU, CHENG-HSIEN CHOU, CHENG-YUAN TSAI, YEUR-LUEN TU
  • Patent number: 9666566
    Abstract: Methods for improving hybrid bond yield for semiconductor wafers forming 3DIC devices includes first and second wafers having dummy and main metal deposited and patterned during BEOL processing. Metal of the dummy metal pattern occupies from about 40% to about 90% of the surface area of any given dummy metal pattern region. High dummy metal surface coverage, in conjunction with utilization of slotted conductive pads, allows for improved planarization of wafer surfaces presented for hybrid bonding. Planarized wafers exhibit minimum topographic differentials corresponding to step height differences of less than about 400 ?. Planarized first and second wafers are aligned and subsequently hybrid bonded with application of heat and pressure; dielectric-to-dielectric, RDL-to-RDL. Lithography controls to realize WEE from about 0.5 mm to about 1.5 mm may also be employed to promote topographic uniformity at wafer edges.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ju-Shi Chen, Cheng-Ying Ho, Chun-Chieh Chuang, Sheng-Chau Chen, Shih Pei Chou, Hui-Wen Shen, Dun-Nian Yaung, Ching-Chun Wang, Feng-Chi Hung, Shyh-Fann Ting
  • Patent number: 9653507
    Abstract: Some embodiments of the present disclosure relate to a deep trench isolation (DTI) structure configured to enhance efficiency and performance of a photovoltaic device. The photovoltaic device comprises a functional layer disposed over an upper surface of a semiconductor substrate, and a pair of pixels formed within the semiconductor substrate, which are separated by the DTI structure. The DTI structure is arranged within a deep trench. Sidewalls of the deep trench are partially covered with a protective sleeve formed along the functional layer prior to etching the deep trench. The protective sleeve prevents etching of the functional layer while etching the deep trench, which prevents contaminants from penetrating the pair of pixels. The protective sleeve also narrows the width of the DTI structure, which increases pixel area and subsequently the efficiency and performance of the photovoltaic device.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hsien Chou, Shih Pei Chou, Chih-Yu Lai, Sheng-Chau Chen, Chih-Ta Chen, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 9627326
    Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Chou, Sheng-Chau Chen, Chun-Wei Chang, Kai-Chun Hsu, Chih-Yu Lai, Wei-Cheng Hsu, Hsiao-Hui Tseng, Shih Pei Chou, Shyh-Fann Ting, Tzu-Hsuan Hsu, Ching-Chun Wang, Yeur-Luen Tu, Dun-Nian Yaung
  • Publication number: 20160379960
    Abstract: The present disclosure relates to a multi-dimensional integrated chip having a redistribution layer vertically extending between integrated chip die, which is laterally offset from a back-side bond pad. The multi-dimensional integrated chip has a first integrated chip die with a first plurality of metal interconnect layers disposed within a first inter-level dielectric layer arranged onto a front-side of a first semiconductor substrate. The multi-dimensional integrated chip also has a second integrated chip die with a second plurality of metal interconnect layers disposed within a second inter-level dielectric layer abutting the first ILD layer. A bond pad is disposed within a recess extending through the second semiconductor substrate. A redistribution layer vertically extends between the first plurality of metal interconnect layers and the second plurality of metal interconnect layers at a position that is laterally offset from the bond pad.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Inventors: Sin-Yao Huang, Chun-Chieh Chuang, Ching-Chun Wang, Sheng-Chau Chen, Dun-Nian Yaung, Feng-Chi Hung, Yung-Lung Lin
  • Publication number: 20160343679
    Abstract: A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the device die is patterned to extend the opening further into the device die. After patterning, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material.
    Type: Application
    Filed: August 4, 2016
    Publication date: November 24, 2016
    Inventors: Sheng-Chau Chen, Shih Pei Chou, Yen-Chang Chu, Cheng-Hsien Chou, Chih-Hui Huang, Yeur-Luen Tu
  • Publication number: 20160276285
    Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.
    Type: Application
    Filed: May 26, 2016
    Publication date: September 22, 2016
    Inventors: Cheng-Hsien Chou, Sheng-Chau Chen, Chun-Wei Chang, Kai-Chun Hsu, Chih-Yu Lai, Wei-Cheng Hsu, Hsiao-Hui Tseng, Shih Pei Chou, Shyh-Fann Ting, Tzu-Hsuan Hsu, Ching-Chun Wang, Yeur-Luen Tu, Dun-Nian Yaung
  • Patent number: 9437572
    Abstract: A method embodiment includes patterning an opening through a layer at a surface of a device die. The method further includes forming a liner on sidewalls of the opening, patterning the device die to extend the opening further into the device die. After patterning the device die, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: September 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chau Chen, Shih Pei Chou, Yen-Chang Chu, Cheng-Hsien Chou, Chih-Hui Huang, Yeur-Luen Tu
  • Patent number: 9355964
    Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Chou, Sheng-Chau Chen, Chun-Wei Chang, Kai-Chun Hsu, Chih-Yu Lai, Wei-Cheng Hsu, Hsiao-Hui Tseng, Shih Pei Chou, Shyh-Fann Ting, Tzu-Hsuan Hsu, Ching-Chun Wang, Yeur-Luen Tu, Dun-Nian Yaung
  • Patent number: 9281331
    Abstract: A vertical-gate transfer transistor of an active pixel sensor (APS) is provided. The transistor includes a semiconductor substrate, a vertical trench extending into the semiconductor substrate, a dielectric lining the vertical trench, and a vertical gate filling the lined vertical trench. The dielectric includes a dielectric constant exceeding 3.9 (i.e., the dielectric constant of silicon dioxide). A method of manufacturing the vertical-gate transfer transistor, an APS including the vertical-gate transfer transistor, a method of manufacturing the APS, and an image sensor including a plurality of the APSs are also provided.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: March 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chau Chen, Chih-Yu Lai, Kuo-Ming Wu, Kuo-Hwa Tzeng, Cheng-Hsien Chou, Cheng-Yuan Tsai, Yeur-Luen Tu, Chia-Shiung Tsai
  • Publication number: 20150380447
    Abstract: Some embodiments of the present disclosure relate to a deep trench isolation (DTI) structure configured to enhance efficiency and performance of a photovoltaic device. The photovoltaic device comprises a functional layer disposed over an upper surface of a semiconductor substrate, and a pair of pixels formed within the semiconductor substrate, which are separated by the DTI structure. The DTI structure is arranged within a deep trench. Sidewalls of the deep trench are partially covered with a protective sleeve formed along the functional layer prior to etching the deep trench. The protective sleeve prevents etching of the functional layer while etching the deep trench, which prevents contaminants from penetrating the pair of pixels. The protective sleeve also narrows the width of the DTI structure, which increases pixel area and subsequently the efficiency and performance of the photovoltaic device.
    Type: Application
    Filed: June 25, 2014
    Publication date: December 31, 2015
    Inventors: Cheng-Hsien Chou, Shih Pei Chou, Chih-Yu Lai, Sheng-Chau Chen, Chih-Ta Chen, Yeur-Luen Tu, Chia-Shiung Tsai
  • Publication number: 20150372034
    Abstract: A vertical-gate transfer transistor of an active pixel sensor (APS) is provided. The transistor includes a semiconductor substrate, a vertical trench extending into the semiconductor substrate, a dielectric lining the vertical trench, and a vertical gate filling the lined vertical trench. The dielectric includes a dielectric constant exceeding 3.9 (i.e., the dielectric constant of silicon dioxide). A method of manufacturing the vertical-gate transfer transistor, an APS including the vertical-gate transfer transistor, a method of manufacturing the APS, and an image sensor including a plurality of the APSs are also provided.
    Type: Application
    Filed: June 19, 2014
    Publication date: December 24, 2015
    Inventors: Sheng-Chau Chen, Chih-Yu Lai, Kuo-Ming Wu, Kuo-Hwa Tzeng, Cheng-Hsien Chou, Cheng-Yuan Tsai, Yeur-Luen Tu, Chia-Shiung Tsai
  • Publication number: 20150255400
    Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 10, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Chou, Sheng-Chau Chen, Chun-Wei Chang, Kai-Chun Hsu, Chih-Yu Lai, Wei-Cheng Hsu, Hsiao-Hui Tseng, Shih Pei Chou, Shyh-Fann Ting, Tzu-Hsuan Hsu, Ching-Chun Wang, Yeur-Luen Tu, Dun-Nian Yaung
  • Publication number: 20150243537
    Abstract: The mechanisms for cleaning a surface of a semiconductor wafer for a hybrid bonding are provided. The method for cleaning a surface of a semiconductor wafer for a hybrid bonding includes providing a semiconductor wafer, and the semiconductor wafer has a conductive pad embedded in an insulating layer. The method also includes performing a plasma process to a surface of the semiconductor wafer, and metal oxide is formed on a surface of the conductive structure. The method further includes performing a cleaning process using a cleaning solution to perform a reduction reaction with the metal oxide, such that metal-hydrogen bonds are formed on the surface of the conductive structure. The method further includes transferring the semiconductor wafer to a bonding chamber under vacuum for hybrid bonding. The mechanisms for a hybrid bonding and a integrated system are also provided.
    Type: Application
    Filed: May 12, 2015
    Publication date: August 27, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Chau CHEN, Chih-Hui HUANG, Yeur-Luen TU, Cheng-Ta WU, Chia-Shiung TSAI, Xiao-Meng CHEN
  • Publication number: 20150214082
    Abstract: An apparatus for and a method of bonding a first substrate and a second substrate are provided. In an embodiment a first wafer chuck has a first curved surface and a second wafer chuck has a second curved surface. A first wafer is placed on the first wafer chuck and a second wafer is placed on a second wafer chuck, such that both the first wafer and the second wafer are pre-warped prior to bonding. Once the first wafer and the second wafer have been pre-warped, the first wafer and the second wafer are bonded together.
    Type: Application
    Filed: January 24, 2014
    Publication date: July 30, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hui Huang, Chun-Han Tsao, Sheng-Chau Chen, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20150214267
    Abstract: Semiconductor devices, image sensors, and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a high dielectric constant (k) insulating material disposed over a workpiece, the high k insulating material having a dielectric constant of greater than about 3.9. A barrier layer is disposed over the high k insulating material. A buffer oxide layer including a porous oxide film is disposed between the high k insulating material and the barrier layer. The porous oxide film has a first porosity, and the barrier layer or the high k insulating material has a second porosity. The first porosity is greater than the second porosity.
    Type: Application
    Filed: January 24, 2014
    Publication date: July 30, 2015
    Inventors: Sheng-Chau Chen, Tung-Ting Wu, Cheng-Ta Wu, Chih-Hui Huang, Yeur-Luen Tu, Jhy-Jyi Sze
  • Publication number: 20150171050
    Abstract: A method embodiment includes patterning an opening through a layer at a surface of a device die. The method further includes forming a liner on sidewalls of the opening, patterning the device die to extend the opening further into the device die. After patterning the device die, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material.
    Type: Application
    Filed: December 18, 2013
    Publication date: June 18, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Chau Chen, Shih Pei Chou, Yen-Chang Chu, Cheng-Hsien Chou, Chih-Hui Huang, Yeur-Luen Tu
  • Patent number: 9040385
    Abstract: Embodiments of mechanisms for cleaning a surface of a semiconductor wafer for a hybrid bonding are provided. The method for cleaning a surface of a semiconductor wafer for a hybrid bonding includes providing a semiconductor wafer, and the semiconductor wafer has a conductive pad embedded in an insulating layer. The method also includes performing a plasma process to a surface of the semiconductor wafer, and metal oxide is formed on a surface of the conductive structure. The method further includes performing a cleaning process using a cleaning solution to perform a reduction reaction with the metal oxide, such that metal-hydrogen bonds are formed on the surface of the conductive structure. The method further includes transferring the semiconductor wafer to a bonding chamber under vacuum for hybrid bonding. Embodiments of mechanisms for a hybrid bonding and a integrated system are also provided.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: May 26, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Chau Chen, Chih-Hui Huang, Yeur-Luen Tu, Cheng-Ta Wu, Chia-Shiung Tsai, Xiao-Meng Chen