Patents by Inventor Sheng-Chen Wang
Sheng-Chen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240138152Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Inventors: Feng-Cheng Yang, Meng-Han Lin, Sheng-Chen Wang, Han-Jong Chia, Chung-Te Lin
-
Patent number: 11968838Abstract: A device includes a semiconductor substrate; a word line extending over the semiconductor substrate; a memory film extending along the word line, wherein the memory film contacts the word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; source lines extending along the memory film, wherein the memory film is between the source lines and the word line; bit lines extending along the memory film, wherein the memory film is between the bit lines and the word line; and isolation regions, wherein each isolation region is between a source line and a bit line, wherein each of the isolation regions includes an air gap and a seal extending over the air gap.Type: GrantFiled: August 30, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Chen Wang, Kai-Hsuan Lee, Sai-Hooi Yeong, Chi On Chui
-
Patent number: 11950428Abstract: A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and conductive pillars. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure.Type: GrantFiled: August 9, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chen Wang, Meng-Han Lin, Sai-Hooi Yeong, Yu-Ming Lin, Han-Jong Chia
-
Publication number: 20240098959Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.Type: ApplicationFiled: November 22, 2023Publication date: March 21, 2024Inventors: Kai-Hsuan Lee, Chia-Ta Yu, Cheng-Yu Yang, Sheng-Chen Wang, Sai-Hooi Yeong, Feng-Cheng Yang, Yen-Ming Chen
-
Publication number: 20240097010Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Inventors: Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen
-
Publication number: 20240088899Abstract: A logic cell structure includes a first portion, a second portion and a third portion. The first portion, arranged to be a first layout of a first semiconductor element, is placed in a first cell row of a substrate area extending in a first direction. The second portion, arranged to be a second layout of a second semiconductor element, is placed in a second cell row of the substrate area. The third portion is arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element. The first, second and third portions are bounded by a bounding box with a height in a second direction and a width in the first direction. Respective centers of the first portion and the second portion are arranged in a third direction different from each of the first direction and the second direction.Type: ApplicationFiled: November 24, 2023Publication date: March 14, 2024Inventors: SHAO-HUAN WANG, CHUN-CHEN CHEN, SHENG-HSIUNG CHEN, KUO-NAN YANG
-
Patent number: 11923433Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.Type: GrantFiled: March 9, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Liang Pan, Yungtzu Chen, Chung-Chieh Lee, Yung-Chang Hsu, Chia-Yang Hung, Po-Chuan Wang, Guan-Xuan Chen, Huan-Just Lin
-
Publication number: 20240064984Abstract: A 3D memory array includes a row of stacks, each stack having alternating gate strips and dielectric strips. Dielectric plugs are disposed between the stacks and define cell areas. A data storage film and a channel film are disposed adjacent the stacks on the sides of the cell areas. The middles of the cell areas are filled with an intracell dielectric. Source lines and drain lines form vias through the intracell dielectric. The source lines and the drain lines are each provided with a bulge toward the interior of the cell area. The bulges increase the areas of the source line and the drain line without reducing the channel lengths. In some of these teachings, the areas of the source lines and the drain lines are increased by restricting the data storage film or the channel layer to the sides of the cell areas adjacent the stacks.Type: ApplicationFiled: October 30, 2023Publication date: February 22, 2024Inventors: Sheng-Chen Wang, Feng-Cheng Yang, Meng-Han Lin, Han-Jong Chia
-
Patent number: 11910616Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.Type: GrantFiled: August 9, 2022Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
-
Patent number: 11903216Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.Type: GrantFiled: May 13, 2022Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Feng-Cheng Yang, Meng-Han Lin, Sheng-Chen Wang, Han-Jong Chia, Chung-Te Lin
-
Publication number: 20240032304Abstract: A memory device, a semiconductor device and a manufacturing method of the memory device are provided. The memory device includes first, second and third stacking structures, first and second channel structures, a gate dielectric layer, a switching layer, and first and second gate structures. The first, second and third stacking structures are laterally spaced apart from one another, and respectively comprise a conductive layer, an isolation layer and a channel layer. The third stacking structure is located between the first and second stacking structures. The first channel structure extends between the channel layers in the first and third stacking structures. The second channel structure extends between the channel layers in the second and third stacking structures. The gate dielectric layer and the first gate structure wrap around the first channel structure. The switching layer and the second gate structure wrap around the second channel structure.Type: ApplicationFiled: April 26, 2023Publication date: January 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Han Lin, Feng-Cheng Yang, Sheng-Chen Wang, Han-Jong Chia
-
Patent number: 11862713Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.Type: GrantFiled: July 28, 2022Date of Patent: January 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen
-
Patent number: 11856743Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.Type: GrantFiled: April 19, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Hsuan Lee, Chia-Ta Yu, Cheng-Yu Yang, Sheng-Chen Wang, Sai-Hooi Yeong, Feng-Cheng Yang, Yen-Ming Chen
-
Publication number: 20230387269Abstract: A semiconductor structure includes a first fin and a second fin protruding from a substrate, isolation features over the substrate to separate the first and the second fins, where a top surface of each of the first and the second fins is below a top surface of the isolation features, inner fin spacers disposed along inner sidewalls of the first and the second fins, where the inner fin spacers have a first height measured from a top surface of the isolation features, outer fin spacers disposed along outer sidewalls of the first and the second fins, where the outer fin spacers have a second height measured from the top surface of the isolation features that is less than the first height, and a source/drain (S/D) structure merging the first and the second fins, where the S/D structure includes an air gap having a top portion over the inner fin spacers.Type: ApplicationFiled: July 26, 2023Publication date: November 30, 2023Inventors: Chia-Ta Yu, Sheng-Chen Wang, Feng-Cheng Yang, Yen-Ming Chen, Sai-Hooi Yeong
-
Publication number: 20230377624Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Inventors: Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
-
Patent number: 11805652Abstract: A 3D memory array includes a row of stacks, each stack having alternating gate strips and dielectric strips. Dielectric plugs are disposed between the stacks and define cell areas. A data storage film and a channel film are disposed adjacent the stacks on the sides of the cell areas. The middles of the cell areas are filled with an intracell dielectric. Source lines and drain lines form vias through the intracell dielectric. The source lines and the drain lines are each provided with a bulge toward the interior of the cell area. The bulges increase the areas of the source line and the drain line without reducing the channel lengths. In some of these teachings, the areas of the source lines and the drain lines are increased by restricting the data storage film or the channel layer to the sides of the cell areas adjacent the stacks.Type: GrantFiled: December 19, 2022Date of Patent: October 31, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chen Wang, Feng-Cheng Yang, Meng-Han Lin, Han-Jong Chia
-
Publication number: 20230339068Abstract: A method of using a polishing pad includes applying a slurry to a first location on the polishing pad. The method further includes rotating the polishing pad. The method further includes spreading the slurry across a first region of the polishing pad at a first rate, wherein the first region includes a plurality of first grooves. The method further includes spreading the slurry across a second region, surrounding the first region of the polishing pad at a second rate different from the first rate, wherein the second region includes a plurality of second grooves. The method further includes spreading the slurry across a third region, surrounding the second region of the polishing pad at a third rate less than the first rate and the second rate, wherein the third region includes a plurality of third grooves.Type: ApplicationFiled: June 26, 2023Publication date: October 26, 2023Inventors: ChunHung CHEN, Jung-Yu LI, Sheng-Chen WANG, Shih-Sian HUANG
-
Publication number: 20230345732Abstract: A memory device, a semiconductor device and manufacturing methods for forming the memory device and the semiconductor device are provided. The memory device includes a stacking structure, a switching layer, channel layers and pairs of conductive pillars. The stacking structure includes alternately stacked isolation layers and word lines, and extends along a first direction. The stacking structure has a staircase portion and a connection portion at an edge region of the stacking structure. The connection portion extends along the staircase portion and located aside the staircase portion, and may not be shaped into a staircase structure. The switching layer covers a sidewall of the stacking structure. The channel layers cover a sidewall of the switching layer, and are laterally spaced apart from one another along the first direction. The pairs of conductive pillars stand on the substrate, and in lateral contact with the switching layer through the channel layers.Type: ApplicationFiled: July 3, 2023Publication date: October 26, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Han Lin, Han-Jong Chia, Yi-Ching Liu, Chia-En Huang, Sheng-Chen Wang, Feng-Cheng Yang, Chung-Te Lin
-
Publication number: 20230330803Abstract: Systems and methods are provided for predicting irregular motions of one or more mechanical components of a semiconductor processing apparatus. A mechanical motion irregular prediction system includes one or more motion sensors that sense motion-related parameters associated with at least one mechanical component of a semiconductor processing apparatus. The one or more motion sensors output sensing signals based on the sensed motion-related parameters. Defect prediction circuitry predicts an irregular motion of the at least one mechanical component based on the sensing signals.Type: ApplicationFiled: June 21, 2023Publication date: October 19, 2023Inventors: Chunhung Chen, Yu Chi Tsai, Chin Wei Chuang, Bo-An Chen, Sheng-Chen Wang, Chen-Hua Tsai
-
Publication number: 20230337436Abstract: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes first and second stacking structures, isolation pillars, gate dielectric layers, channel layers and conductive pillars. The stacking structures are laterally spaced apart from each other. The stacking structures respectively comprises alternately stacked insulating layers and conductive layers. The isolation pillars laterally extend between the stacking structures. The isolation pillars further protrude into the stacking structures, and a space between the stacking structures is divided into cell regions. The gate dielectric layers are respectively formed in one of the cell regions, and cover opposing sidewalls of the stacking structures and sidewalls of the isolation pillars. The channel layers respectively cover an inner surface of one of the gate dielectric layers.Type: ApplicationFiled: June 21, 2023Publication date: October 19, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Han Lin, Chun-Fu Cheng, Feng-Cheng Yang, Sheng-Chen Wang, Yu-Chien Chiu, Han-Jong Chia