Patents by Inventor Sheng-Chen Wang

Sheng-Chen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210375938
    Abstract: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes first and second stacking structures, isolation pillars, gate dielectric layers, channel layers and conductive pillars. The stacking structures are laterally spaced apart from each other. The stacking structures respectively comprises alternately stacked insulating layers and conductive layers. The isolation pillars laterally extend between the stacking structures. The isolation pillars further protrude into the stacking structures, and a space between the stacking structures is divided into cell regions. The gate dielectric layers are respectively formed in one of the cell regions, and cover opposing sidewalls of the stacking structures and sidewalls of the isolation pillars. The channel layers respectively cover an inner surface of one of the gate dielectric layers.
    Type: Application
    Filed: January 26, 2021
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Han Lin, Chun-Fu Cheng, Feng-Cheng Yang, Sheng-Chen Wang, Yu-Chien Chiu, Han-Jong Chia
  • Barrier layer above anti-punch through (APT) implant region to improve mobility of channel region of fin field effect transistor (finFET) device structure
    Patent number: 11158508
    Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a protruding structure extending from a substrate and an anti-punch through implant (APT) region formed in the protruding structure. The FinFET device structure includes a barrier layer formed on the APT region, and the barrier layer has a width in a horizontal direction. The width gradually tapers from a bottom of the barrier layer to a top of the barrier layer.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Yao Wen, Sheng-Chen Wang, Sai-Hooi Yeong, Hsueh-Chang Sung, Ya-Yun Cheng
  • Forming transistor by selectively growing gate spacer
    Patent number: 11133229
    Abstract: A method includes forming a gate dielectric layer on a semiconductor fin, and forming a gate electrode over the gate dielectric layer. The gate electrode extends on sidewalls and a top surface of the semiconductor fin. A gate spacer is selectively deposited on a sidewall of the gate electrode. An exposed portion of the gate dielectric layer is free from a same material for forming the gate spacer deposited thereon. The method further includes etching the gate dielectric layer using the gate spacer as an etching mask to expose a portion of the semiconductor fin, and forming an epitaxy semiconductor region based on the semiconductor fin.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Hsuan Lee, Chia-Ta Yu, Cheng-Yu Yang, Sheng-Chen Wang, Bo-Yu Lai, Bo-Cyuan Lu, Chi On Chui, Sai-Hooi Yeong, Feng-Cheng Yang, Yen-Ming Chen
  • Semiconductor device including fin structures and manufacturing method thereof
    Patent number: 11133306
    Abstract: A semiconductor device includes device areas where a Fin FET is disposed and a non-device area disposed between the device areas, which includes a dummy structure. The Fin FET includes a fin structure having a well region including a first semiconductor layer, a stressor region including a second semiconductor layer and a channel region including a third semiconductor layer; an isolation region in which the well region is embedded, and from which at least an upper port of the channel region is exposed; a gate structure disposed over a part of the fin structure. The dummy structure in the non-device area includes a first dummy layer formed over the first semiconductor layer and made of a different material from the stressor region, and a second dummy layer formed over the first dummy layer and made of a different material from the channel region.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: September 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Chen Wang, Sai-Hooi Yeong, Tsung-Chieh Hsiao
  • Epitaxial Structures for Fin-Like Field Effect Transistors
    Publication number: 20210280696
    Abstract: A semiconductor structure includes a first fin and a second fin protruding from a substrate, isolation features over the substrate to separate the first and the second fins, where a top surface of each of the first and the second fins is below a top surface of the isolation features, inner fin spacers disposed along inner sidewalls of the first and the second fins, where the inner fin spacers have a first height measured from a top surface of the isolation features, outer fin spacers disposed along outer sidewalls of the first and the second fins, where the outer fin spacers have a second height measured from the top surface of the isolation features that is less than the first height, and a source/drain (S/D) structure merging the first and the second fins, where the S/D structure includes an air gap having a top portion over the inner fin spacers.
    Type: Application
    Filed: May 19, 2021
    Publication date: September 9, 2021
    Inventors: Chia-Ta Yu, Sheng-Chen Wang, Feng-Cheng Yang, Yen-Ming Chen, Sai-Hooi Yeong
  • Flexible Merge Scheme for Source/Drain Epitaxy Regions
    Publication number: 20210242217
    Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.
    Type: Application
    Filed: April 19, 2021
    Publication date: August 5, 2021
    Inventors: Kai-Hsuan Lee, Chia-Ta Yu, Cheng-Yu Yang, Sheng-Chen Wang, Sai-Hooi Yeong, Feng-Cheng Yang, Yen-Ming Chen
  • PAD REMOVAL METHOD
    Publication number: 20210229415
    Abstract: A pad removal method includes affixing a first end of a pad guide to a first edge location of a pad. The pad removal method further includes affixing a second end of the pad guide to a second edge location of the pad. The pad removal method further includes moving the first end from a first position, a first distance from the second edge location, to a second position, a second distance from the second edge location, wherein the first distance is greater than a diameter of the pad, and the second distance is less than the diameter of the pad.
    Type: Application
    Filed: April 13, 2021
    Publication date: July 29, 2021
    Inventors: ChunHung CHEN, Sheng-Chen WANG
  • Epitaxial structures for fin-like field effect transistors
    Patent number: 11018245
    Abstract: A method includes forming a first fin and a second fin protruding from a semiconductor substrate and defined by a fin height, forming a spacer layer over the first fin and the second fin, etching the spacer layer to form inner spacers and outer spacers along opposite sidewalls of each of the first fin and the second fin, where the inner spacers are formed between the first fin and the second fin and where etching the spacer layer results in the inner spacers to extend above the outer spacers, forming a source/drain (S/D) recess in each of the first fin and the second fin, and forming an epitaxial semiconductor layer in the S/D recesses, where forming the epitaxial semiconductor layer forms an air gap with the inner spacers.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ta Yu, Sheng-Chen Wang, Feng-Cheng Yang, Yen-Ming Chen, Sai-Hooi Yeong
  • Semiconductor device with epitaxial source/drain
    Patent number: 11018224
    Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. In some embodiments, the semiconductor device includes a fin extending from a substrate and a gate structure disposed over the fin. The gate structure includes a gate dielectric formed over the fin, a gate electrode formed over the gate dielectric, and a sidewall spacer formed along a sidewall of the gate electrode. In some cases, a U-shaped recess is within the fin and adjacent to the gate structure. A first source/drain layer is conformally formed on a surface of the U-shaped recess, where the first source/drain layer extends at least partially under the adjacent gate structure. A second source/drain layer is formed over the first source/drain layer. At least one of the first and second source/drain layers includes silicon arsenide (SiAs).
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ta Yu, Sheng-Chen Wang, Wei-Yuan Lu, Chien-I Kuo, Li-Li Su, Feng-Cheng Yang, Yen-Ming Chen, Sai-Hooi Yeong
  • Conformal Transfer Doping Method for Fin-Like Field Effect Transistor
    Publication number: 20210134985
    Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.
    Type: Application
    Filed: December 14, 2020
    Publication date: May 6, 2021
    Inventors: Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen
  • Pad removal device and method
    Patent number: 10987913
    Abstract: A pad removal device includes a pad guide extending along a first direction. The pad guide includes a first affixing component configured to affix a first end of the pad guide to a pad at a first pad edge location, and a second affixing component configured to affix a second end of the pad guide to the pad at a second pad edge location opposite the first pad edge location. The pad removal device further includes an actuator attached to the pad guide, and a control assembly coupled to the actuator and configured to cause the actuator to move the first end toward the second end along the first direction. The pad guide is configured to extend in a second direction different from the first direction by an amount dependent on a distance between the first end and the second end.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: ChunHung Chen, Sheng-Chen Wang
  • Flexible merge scheme for source/drain epitaxy regions
    Patent number: 10985167
    Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Hsuan Lee, Chia-Ta Yu, Cheng-Yu Yang, Sheng-Chen Wang, Sai-Hooi Yeong, Feng-Cheng Yang, Yen-Ming Chen
  • METHOD OF USING POLISHING PAD
    Publication number: 20210069855
    Abstract: A method of using a polishing pad includes applying a slurry to a first location on the polishing pad. The method further includes rotating the polishing pad. The method further includes spreading the slurry across a first region of the polishing pad at a first rate, wherein the first region includes a plurality of first grooves, a first material property of the first region varies in a thickness direction of the polishing pad, each of the plurality of first grooves extends through at least two variations in the first material property, and the first material property comprises porosity, specific gravity or absorbance. The method further includes spreading the slurry across a second region of the polishing pad at a second rate different from the first rate, wherein the second region comprises a plurality of second grooves.
    Type: Application
    Filed: November 19, 2020
    Publication date: March 11, 2021
    Inventors: ChunHung CHEN, Jung-Yu LI, Sheng-Chen WANG, Shih-Sian HUANG
  • SEMICONDUCTOR DEVICE HAVING A UNIFORM AND THIN SILICIDE LAYER ON AN EPITAXIAL SOURCE/ DRAIN STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210035806
    Abstract: In a method of manufacturing a semiconductor device, a first layer containing an amorphous first material is formed by a deposition process over a semiconductor layer. A second layer containing a metal second material is formed over the first layer. A thermal process is performed to form an alloy layer of the amorphous first material and the metal second material.
    Type: Application
    Filed: October 19, 2020
    Publication date: February 4, 2021
    Inventors: Kai-Hsuan LEE, Jyh-Cherng SHEU, Sung-Li WANG, Cheng-Yu YANG, Sheng-Chen WANG, Sai-Hooi YEONG
  • Semiconductor device and manufacturing method thereof
    Patent number: 10879374
    Abstract: A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. A width of the separation plug in a second direction perpendicular to the first direction is smaller than a width of the first gate structure in the second direction, when viewed in plan view.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hao Yu, Sheng-Chen Wang, Sai-Hooi Yeong
  • FinFET transistor with fin back biasing
    Patent number: 10868006
    Abstract: A method of forming a semiconductor device includes forming a fin protruding from a substrate, the fin having a channel region, a source/drain (S/D) region, and a biasing region, wherein the channel region and the biasing region sandwich the S/D region. The method further includes trimming the biasing region to reduce a height of the biasing region and forming a gate structure engaging the channel region. The method also includes forming a conductive feature electrically coupling to the biasing region.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Yao Wen, Sai-Hooi Yeong, Sheng-chen Wang
  • Polishing pad and method of using
    Patent number: 10864612
    Abstract: A polishing pad includes a first region having a first geometric property and a first material property. The polishing pad further includes a second region having a second geometric property and a second material property, wherein the second region is closer to an edge of the polishing pad than the first region. The first geometric property is different from the second geometric property; or the first material property is different from the second material property.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: ChunHung Chen, Jung-Yu Li, Sheng-Chen Wang, Shih-Sian Huang
  • Conformal transfer doping method for fin-like field effect transistor
    Patent number: 10868151
    Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen
  • Semiconductor device having a uniform and thin silicide layer on an epitaxial source/ drain structure and manufacturing method thereof
    Patent number: 10811262
    Abstract: In a method of manufacturing a semiconductor device, a first layer containing an amorphous first material is formed by a deposition process over a semiconductor layer. A second layer containing a metal second material is formed over the first layer. A thermal process is performed to form an alloy layer of the amorphous first material and the metal second material.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Hsuan Lee, Jyh-Cherng Sheu, Sung-Li Wang, Cheng-Yu Yang, Sheng-Chen Wang, Sai-Hooi Yeong
  • Epitaxial Structures for Fin-Like Field Effect Transistors
    Publication number: 20200303522
    Abstract: A method includes forming a first fin and a second fin protruding from a semiconductor substrate and defined by a fin height, forming a spacer layer over the first fin and the second fin, etching the spacer layer to form inner spacers and outer spacers along opposite sidewalls of each of the first fin and the second fin, where the inner spacers are formed between the first fin and the second fin and where etching the spacer layer results in the inner spacers to extend above the outer spacers, forming a source/drain (S/D) recess in each of the first fin and the second fin, and forming an epitaxial semiconductor layer in the S/D recesses, where forming the epitaxial semiconductor layer forms an air gap with the inner spacers.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Inventors: Chia-Ta Yu, Sheng-Chen Wang, Feng-Cheng Yang, Yen-Ming Chen, Sai-Hooi Yeong