Patents by Inventor Sheng Cheng
Sheng Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240139734Abstract: A biological particle enrichment apparatus and a pico-droplet generator thereof are provided. The pico-droplet generator includes a container, a hollow needle connected to the container, a first piezoelectric member disposed on the container, and a second piezoelectric member disposed on the hollow needle. The container can receive a liquid specimen having biological particles. The hollow needle and the container are fluid communicated with each other, and an inner diameter of the container is within a range from 5 times to 30 times of an inner diameter of the hollow needle. The first piezoelectric member is annularly disposed on a surrounding lateral side of the container, and enables the biological particles in the container to move along a direction away from the surrounding lateral side by vibrating the container. The second piezoelectric member can squeeze the hollow needle, so that the liquid specimen flows outwardly to form a pico-droplet.Type: ApplicationFiled: April 10, 2023Publication date: May 2, 2024Inventors: Chung-Er Huang, Sheng-Wen Chen, Hsin-Cheng Ho, GUANG-CI YE
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Publication number: 20240142727Abstract: An optoelectronic device includes a photonic component. The photonic component includes an active side, a second side different from the active side, and an optical channel extending from the active side to the second side of the photonic component. The optical channel includes a non-gaseous material configured to transmit light.Type: ApplicationFiled: January 9, 2024Publication date: May 2, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Jr-Wei LIN, Sin-Yuan MU, Chia-Sheng CHENG
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Publication number: 20240142459Abstract: A biological particle analysis method is provided and includes the following steps: fluorescence staining a liquid specimen through a fluorescence staining process so as to enable a target biological particle in the liquid specimen to becomes a fluorescence; accommodating the liquid specimen into a pico-droplet generator and using a camera device to take a real-time image of the liquid specimen; using the pico-droplet generator to output a target pico-droplet having the target biological particle onto a biochip according to the real-time image; removing the fluorescent color of the target biological particle in the target pico-droplet through a washing process; and fluorescence staining the target biological particle captured by the biochip at multiple times through the fluorescence staining process and the washing process, so as to obtain a plurality of fluorescence images respectively corresponding to multiple kinds of biological characterization expressions.Type: ApplicationFiled: April 10, 2023Publication date: May 2, 2024Inventors: Chung-Er Huang, Sheng-Wen Chen, Hsin-Cheng Ho, GUANG-CI YE
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Patent number: 11973095Abstract: A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.Type: GrantFiled: July 8, 2022Date of Patent: April 30, 2024Assignee: XINTEC INC.Inventors: Kuei-Wei Chen, Chia-Ming Cheng, Chia-Sheng Lin
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Publication number: 20240136316Abstract: A semiconductor package includes a conductive pillar and a solder. The conductive pillar has a first sidewall and a second sidewall opposite to the first sidewall, wherein a height of the first sidewall is greater than a height of the second sidewall. The solder is disposed on and in direct contact with the conductive pillar, wherein the solder is hanging over the first sidewall and the second sidewall of conductive pillar.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chiang-Jui Chu, Ching-Wen Hsiao, Hao-Chun Liu, Ming-Da Cheng, Young-Hwa Wu, Tao-Sheng Chang
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Publication number: 20240138152Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Inventors: Feng-Cheng Yang, Meng-Han Lin, Sheng-Chen Wang, Han-Jong Chia, Chung-Te Lin
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Patent number: 11967375Abstract: A memory device that includes at least one memory cell is introduced. Each of the at least one memory cell is coupled to a bit line and a word line. Each of the at least one memory cell includes a memory element and a selector element, in which the memory element is configured to store data of the at least one memory cell. The selector element is coupled to the memory element in series and is configured to select the memory element for a read operation and amplify the data stored in the memory element in the read operation.Type: GrantFiled: November 18, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Li Chiang, Chao-Ching Cheng, Tzu-Chiang Chen, Yu-Sheng Chen, Hon-Sum Philip Wong
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Publication number: 20240124163Abstract: A magnetic multi-pole propulsion array system is applied to at least one external cathode and includes a plurality of magnetic multi-pole thrusters connected adjacent to each other. Each magnetic multi-pole thruster includes a propellant provider, a discharge chamber, an anode and a plurality of magnetic components. The propellant provider outputs propellant. The discharge chamber is connected with the propellant provider to accommodate the propellant. The anode is disposed inside the discharge chamber to generate an electric field. The plurality of magnetic components is respectively disposed on several sides of the discharge chamber. One of the several sides of the discharge chamber of the magnetic multi-pole thruster is applied for one side of a discharge chamber of another magnetic multi-pole thruster.Type: ApplicationFiled: December 19, 2022Publication date: April 18, 2024Applicant: National Cheng Kung UniversityInventors: Yueh-Heng Li, Yu-Ting Wu, Chao-Wei Huang, Wei-Cheng Lo, Hsun-Chen Hsieh, Ping-Han Huang, Yi-Long Huang, Sheng-Wen Liu, Wei-Cheng Lien
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Publication number: 20240123434Abstract: A multifunctional catalyst, a method for producing the same, and a method for using the same are provided. The multifunctional catalyst is applicable for recycling a polyester fabric. The multifunctional catalyst includes a carrier, and a first functional ionic liquid and a second functional ionic liquid that are grafted on the carrier. The carrier is an inorganic composite powder material, and is composed of following chemical components: C: Na—Ni/Al2O3. In a process of recycling the polyester fabric, the multifunctional catalyst simultaneously decolorizes and depolymerizes the polyester fabric. The first functional ionic liquid is used to decolorize the polyester fabric, and the second functional ionic liquid is used to depolymerize the polyester fabric.Type: ApplicationFiled: December 12, 2022Publication date: April 18, 2024Inventors: TE-CHAO LIAO, WEI-SHENG CHENG, YU-LIN LI
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Publication number: 20240124456Abstract: An aza-ergoline derivative and a preparation method therefor and an application thereof. The derivative has a structure as shown in formula (I). The aza-ergoline derivative has good affinity, agonistic activity or selectivity to a dopamine D2 receptor.Type: ApplicationFiled: January 29, 2022Publication date: April 18, 2024Inventors: Jianjun CHENG, Sheng WANG, Huan WANG, Luyu FAN, Zhangcheng CHEN, Jing YU, Jianzhong QI, Fen NIE
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Patent number: 11962014Abstract: Electrodeposited copper foils having adequate puncture strength to withstand both pressure application during consolidation with negative electrode active materials during manufacture, as well as expansion/contraction during repeated charge/discharging cycles when used in a rechargeable secondary battery are described. These copper foils find specific utility as current collectors in rechargeable secondary batteries, particularly in lithium secondary battery with high capacity. Methods of making the copper foils, methods of producing negative electrode for use in lithium secondary battery and lithium secondary battery of high capacity are also described.Type: GrantFiled: December 17, 2018Date of Patent: April 16, 2024Assignee: CHANG CHUN PETROCHEMICAL CO., LTD.Inventors: Huei-Fang Huang, Kuei-Sen Cheng, Yao-Sheng Lai, Jui-Chang Chou
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Patent number: 11963369Abstract: The present disclosure relates to an integrated circuit. The integrated circuit has a plurality of bit-line stacks disposed over a substrate and respectively including a plurality of bit-lines stacked onto one another. A data storage structure is over the plurality of bit-line stacks and a selector is over the data storage structure. A word-line is over the selector. The selector is configured to selectively allow current to pass between the plurality of bit-lines and the word-line. The plurality of bit-line stacks include a first bit-line stack, a second bit-line stack, and a third bit-line stack. The first and third bit-line stacks are closest bit-line stacks to opposing sides of the second bit-line stack. The second bit-line stack is separated from the first bit-line stack by a first distance and is further separated from the third bit-line stack by a second distance larger than the first distance.Type: GrantFiled: July 27, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Li Chiang, Chao-Ching Cheng, Jung-Piao Chiu, Tzu-Chiang Chen, Yu-Sheng Chen
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Patent number: 11955507Abstract: A light-emitting device, including a first type semiconductor layer, a patterned insulating layer, a light-emitting layer, and a second type semiconductor layer, is provided. The patterned insulating layer covers the first type semiconductor layer and has a plurality of insulating openings. The insulating openings are separated from each other. The light-emitting layer is located in the plurality of insulating openings and covers a portion of the first type semiconductor layer. The second type semiconductor layer is located on the light-emitting layer.Type: GrantFiled: September 9, 2021Date of Patent: April 9, 2024Assignee: AU OPTRONICS CORPORATIONInventors: Hsin-Hung Li, Wei-Syun Wang, Chih-Chiang Chen, Yu-Cheng Shih, Cheng-Chan Wang, Chia-Hsin Chung, Ming-Jui Wang, Sheng-Ming Huang
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Patent number: 11955423Abstract: Methods for forming dummy under-bump metallurgy structures and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a second passivation layer over the first passivation layer; a first under-bump metallurgy (UBM) structure over the first redistribution line, the first UBM structure extending through the first passivation layer and the second passivation layer and being electrically coupled to the first redistribution line; and a second UBM structure over the second redistribution line, the second UBM structure extending through the second passivation layer, the second UBM structure being electrically isolated from the second redistribution line by the first passivation layer.Type: GrantFiled: March 26, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ting-Li Yang, Po-Hao Tsai, Ming-Da Cheng, Yung-Han Chuang, Hsueh-Sheng Wang
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Patent number: 11953448Abstract: A method for defect inspection includes receiving a substrate having a plurality of patterns; obtaining a gray scale image of the substrate, wherein the gray scale image includes a plurality of regions, and each of the regions has a gray scale value; comparing the gray scale value of each region to a gray scale references to define a first group, a second group and an Nth group, wherein each of the first group, the second group and the Nth group has at least a region; performing a calculation to obtain a score; and when the score is greater than a value, the substrate is determined to have an ESD defect, and when the score is less than the value, the substrate is determined to be free of the ESD defect.Type: GrantFiled: April 7, 2020Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tsun-Cheng Tang, Hao-Ming Chang, Sheng-Chang Hsu, Cheng-Ming Lin
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Publication number: 20240114405Abstract: A method and an apparatus are provided in which a user equipment (UE) connected with a serving cell performs a random access channel (RACH) procedure for a non-serving cell. The UE acquires a time advance (TA) of the non-serving cell based on the RACH procedure. The UE performs an L1/L2-based handover from the serving cell to the non-serving cell with the acquired TA.Type: ApplicationFiled: August 10, 2023Publication date: April 4, 2024Inventors: Yuan-sheng CHENG, Jung Hyun BAE
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Patent number: 11945766Abstract: The present invention relates to the technical field of acetonitrile refining, and in particular, to an improved acetonitrile purification process for an ultrahigh performance liquid chromatography-mass spectrometer. The present invention provides an acetonitrile purification process. A high-purity finished product may be obtained by performing operations of oxidation, rectification adsorption, drying, reflux rectification and filtration on industrial acetonitrile and controlling related parameters such as temperature, flow and the like, continuous production is ensured, a light transmittance of the finished product in ultraviolet rays of 200 to 260 nm is greater than or equal to 95%, water and impurities in the industrial acetonitrile are removed, and the requirements of the ultrahigh performance liquid chromatography-mass spectrometer are met; moreover, by controlling process parameters and equipment.Type: GrantFiled: May 7, 2020Date of Patent: April 2, 2024Inventors: Sheng Wen, ZhengChong Zhao, ChunLi Gong, Fan Cheng, Hai Liu, FuQiang Hu
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Patent number: 11948941Abstract: A semiconductor device includes a gate layer, a channel material layer, a first dielectric layer and source/drain terminals. The gate layer is disposed over a substrate. The channel material layer is disposed over the gate layer, where a material of the channel material layer includes a first low dimensional material. The first dielectric layer is between the gate layer and the channel material layer. The source/drain terminals are in contact with the channel material layer, where the channel material layer is at least partially disposed between the source/drain terminals and over the gate layer, and the gate layer is disposed between the substrate and the source/drain terminals.Type: GrantFiled: June 23, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Tse Hung, Ang-Sheng Chou, Hung-Li Chiang, Tzu-Chiang Chen, Chao-Ching Cheng
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Publication number: 20240105631Abstract: Embodiments provide a method of performing a carrier switch for a device wafer, attaching a second wafer and removing a first wafer. A buffer layer is deposited over the device wafer, buffer layer reducing the topography of the surface of the device wafer. After the carrier switch a film-on-wire layer is removed from the buffer layer and then the buffer layer is at least in part removed.Type: ApplicationFiled: January 10, 2023Publication date: March 28, 2024Inventors: Jeng-An Wang, Sheng-Chi Lin, Hao-Cheng Hou, Tsung-Ding Wang, Chien-Hsun Lee
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Publication number: 20240100575Abstract: A circuit board cleaning system includes a cleaning tank, an ion exchange resin column, and a pump unit. The cleaning tank accommodates a cleaning liquid and allows a circuit board to be immersed in the cleaning liquid. The cleaning liquid includes a liquid water and a hydrocarbon-based surfactant. An ion exchange resin filled in the ion exchange resin column is a basic ion exchange resin. The pump unit is configured to pump the cleaning liquid into the ion exchange resin column, and enable the cleaning liquid to pass through the ion exchange resin column. When the cleaning liquid passes through the ion exchange resin column, the basic ion exchange resin deprotonates the hydrocarbon-based surfactant. After the cleaning liquid passes through the ion exchange resin column, the cleaning liquid is returned to the cleaning tank to remove acidic residue remaining on a surface of the circuit board.Type: ApplicationFiled: December 12, 2022Publication date: March 28, 2024Inventors: TE-CHAO LIAO, WEI-SHENG CHENG, CHAO-TUNG WU