Abstract: A magnetic multi-pole propulsion array system is applied to at least one external cathode and includes a plurality of magnetic multi-pole thrusters connected adjacent to each other. Each magnetic multi-pole thruster includes a propellant provider, a discharge chamber, an anode and a plurality of magnetic components. The propellant provider outputs propellant. The discharge chamber is connected with the propellant provider to accommodate the propellant. The anode is disposed inside the discharge chamber to generate an electric field. The plurality of magnetic components is respectively disposed on several sides of the discharge chamber. One of the several sides of the discharge chamber of the magnetic multi-pole thruster is applied for one side of a discharge chamber of another magnetic multi-pole thruster.

Abstract: A multifunctional catalyst, a method for producing the same, and a method for using the same are provided. The multifunctional catalyst is applicable for recycling a polyester fabric. The multifunctional catalyst includes a carrier, and a first functional ionic liquid and a second functional ionic liquid that are grafted on the carrier. The carrier is an inorganic composite powder material, and is composed of following chemical components: C: Na—Ni/Al2O3. In a process of recycling the polyester fabric, the multifunctional catalyst simultaneously decolorizes and depolymerizes the polyester fabric. The first functional ionic liquid is used to decolorize the polyester fabric, and the second functional ionic liquid is used to depolymerize the polyester fabric.

Abstract: The present disclosure relates to an integrated circuit. The integrated circuit has a plurality of bit-line stacks disposed over a substrate and respectively including a plurality of bit-lines stacked onto one another. A data storage structure is over the plurality of bit-line stacks and a selector is over the data storage structure. A word-line is over the selector. The selector is configured to selectively allow current to pass between the plurality of bit-lines and the word-line. The plurality of bit-line stacks include a first bit-line stack, a second bit-line stack, and a third bit-line stack. The first and third bit-line stacks are closest bit-line stacks to opposing sides of the second bit-line stack. The second bit-line stack is separated from the first bit-line stack by a first distance and is further separated from the third bit-line stack by a second distance larger than the first distance.

Abstract: Electrodeposited copper foils having adequate puncture strength to withstand both pressure application during consolidation with negative electrode active materials during manufacture, as well as expansion/contraction during repeated charge/discharging cycles when used in a rechargeable secondary battery are described. These copper foils find specific utility as current collectors in rechargeable secondary batteries, particularly in lithium secondary battery with high capacity. Methods of making the copper foils, methods of producing negative electrode for use in lithium secondary battery and lithium secondary battery of high capacity are also described.

Abstract: Methods for forming dummy under-bump metallurgy structures and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a second passivation layer over the first passivation layer; a first under-bump metallurgy (UBM) structure over the first redistribution line, the first UBM structure extending through the first passivation layer and the second passivation layer and being electrically coupled to the first redistribution line; and a second UBM structure over the second redistribution line, the second UBM structure extending through the second passivation layer, the second UBM structure being electrically isolated from the second redistribution line by the first passivation layer.

Abstract: A method for defect inspection includes receiving a substrate having a plurality of patterns; obtaining a gray scale image of the substrate, wherein the gray scale image includes a plurality of regions, and each of the regions has a gray scale value; comparing the gray scale value of each region to a gray scale references to define a first group, a second group and an Nth group, wherein each of the first group, the second group and the Nth group has at least a region; performing a calculation to obtain a score; and when the score is greater than a value, the substrate is determined to have an ESD defect, and when the score is less than the value, the substrate is determined to be free of the ESD defect.

Abstract: A light-emitting device, including a first type semiconductor layer, a patterned insulating layer, a light-emitting layer, and a second type semiconductor layer, is provided. The patterned insulating layer covers the first type semiconductor layer and has a plurality of insulating openings. The insulating openings are separated from each other. The light-emitting layer is located in the plurality of insulating openings and covers a portion of the first type semiconductor layer. The second type semiconductor layer is located on the light-emitting layer.

Abstract: A method and an apparatus are provided in which a user equipment (UE) connected with a serving cell performs a random access channel (RACH) procedure for a non-serving cell. The UE acquires a time advance (TA) of the non-serving cell based on the RACH procedure. The UE performs an L1/L2-based handover from the serving cell to the non-serving cell with the acquired TA.

Abstract: The present invention relates to the technical field of acetonitrile refining, and in particular, to an improved acetonitrile purification process for an ultrahigh performance liquid chromatography-mass spectrometer. The present invention provides an acetonitrile purification process. A high-purity finished product may be obtained by performing operations of oxidation, rectification adsorption, drying, reflux rectification and filtration on industrial acetonitrile and controlling related parameters such as temperature, flow and the like, continuous production is ensured, a light transmittance of the finished product in ultraviolet rays of 200 to 260 nm is greater than or equal to 95%, water and impurities in the industrial acetonitrile are removed, and the requirements of the ultrahigh performance liquid chromatography-mass spectrometer are met; moreover, by controlling process parameters and equipment.

Abstract: A semiconductor device includes a gate layer, a channel material layer, a first dielectric layer and source/drain terminals. The gate layer is disposed over a substrate. The channel material layer is disposed over the gate layer, where a material of the channel material layer includes a first low dimensional material. The first dielectric layer is between the gate layer and the channel material layer. The source/drain terminals are in contact with the channel material layer, where the channel material layer is at least partially disposed between the source/drain terminals and over the gate layer, and the gate layer is disposed between the substrate and the source/drain terminals.

Abstract: A circuit board cleaning system includes a cleaning tank, an ion exchange resin column, and a pump unit. The cleaning tank accommodates a cleaning liquid and allows a circuit board to be immersed in the cleaning liquid. The cleaning liquid includes a liquid water and a hydrocarbon-based surfactant. An ion exchange resin filled in the ion exchange resin column is a basic ion exchange resin. The pump unit is configured to pump the cleaning liquid into the ion exchange resin column, and enable the cleaning liquid to pass through the ion exchange resin column. When the cleaning liquid passes through the ion exchange resin column, the basic ion exchange resin deprotonates the hydrocarbon-based surfactant. After the cleaning liquid passes through the ion exchange resin column, the cleaning liquid is returned to the cleaning tank to remove acidic residue remaining on a surface of the circuit board.

Abstract: Embodiments provide a method of performing a carrier switch for a device wafer, attaching a second wafer and removing a first wafer. A buffer layer is deposited over the device wafer, buffer layer reducing the topography of the surface of the device wafer. After the carrier switch a film-on-wire layer is removed from the buffer layer and then the buffer layer is at least in part removed.

Abstract: The disclosure provides a limit device and a robot using the same. The limit device comprises a first connecting member, a transmission rod and a second connecting member. The first connecting member comprising a first main body portion and two first connecting elements. The two first connecting elements are arranged at intervals. The two first connecting elements are respectively connected to the first main body. The transmission rod comprising a first end and a second end. The first end and the second end are arranged at intervals. The first end penetrates through one of the two first connecting elements. The second end penetrates through the other one of the two first connecting element. The second connecting member provided with two indexing buckles. The two indexing buckles are arranged at intervals, each of the indexing buckles comprises a first limiting groove and a second limiting groove.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate and a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate from a lower surface of the conductive pillar. The semiconductor device structure also includes an upper conductive via between the conductive pillar and the interconnection structure and a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via. The conductive pillar extends across opposite sidewalls of the upper conductive via and opposite sidewalls of the lower conductive via. A top view of an entirety of the second conductive via is separated from a top view of an entirety of the protruding portion.

Abstract: The present invention relates to extended recombinant polypeptide (XTEN) compositions, conjugate compositions comprising XTEN and XTEN linked to cross-linkers useful for conjugation to pharmacologically active payloads, methods of making highly purified XTEN, methods of making XTEN-linker and XTEN-payload conjugates, and methods of using the XTEN-cross-linker and XTEN-payload compositions.

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

Abstract: In order to reduce the occurrence of current alarms in a semiconductor etching or deposition process, a controller determines an offset in relative positions of a cover ring and a shield over a wafer within a vacuum chamber. The controller provides a position alarm and/or adjusts the position of the cover ring or shield when the offset is greater than a predetermined value or outside a range of acceptable values.

Abstract: A radar signal processing system with a self-interference cancelling function includes an analog front end (AFE) processor, an analog to digital converter (ADC), an adaptive interference canceller (AIC), and a digital to analog converter (DAC). The AFE processor receives an original input signal and generates an analog input signal. The ADC converts the analog input signal to a digital input signal. The AIC generates a digital interference signal digital interference signal by performing an adaptive interference cancellation process according to the digital input signal. The DAC converts the digital interference signal to an analog interference signal. Finally, the analog interference signal is fed back to the AFE and cancelled from the original input signal in the AFE processor while performing the front end process, reducing the interference of the static interference from the leaking of a close-by transmitter during the front end process.

Abstract: Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.