Patents by Inventor Sheng-Chi Chin

Sheng-Chi Chin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230366857
    Abstract: Methods and systems disclosed herein use acoustic energy to determine a gap between a wafer and an integrated circuit (IC) processing system and/or determine a thickness of a material layer of the wafer during IC processing implemented by the IC processing system. An exemplary method includes emitting acoustic energy through a substrate and a material layer disposed thereover. The substrate is positioned within an IC processing system. The method further includes receiving reflected acoustic energy from a surface of the substrate and a surface of the material layer disposed thereover and converting the reflected acoustic energy into electrical signals. The electrical signals indicate a thickness of the material layer.
    Type: Application
    Filed: July 19, 2023
    Publication date: November 16, 2023
    Inventors: Jun-Hao Deng, Kuan-Wen Lin, Sheng-Chi Chin, Yu-Ching Lee
  • Patent number: 11709153
    Abstract: Methods and systems disclosed herein use acoustic energy to determine a gap between a wafer and an integrated circuit (IC) processing system and/or determine a thickness of a material layer of the wafer during IC processing implemented by the IC processing system. An exemplary method includes emitting acoustic energy through a substrate and a material layer disposed thereover. The substrate is positioned within an IC processing system. The method further includes receiving reflected acoustic energy from a surface of the substrate and a surface of the material layer disposed thereover and converting the reflected acoustic energy into electrical signals. The electrical signals indicate a thickness of the material layer.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: July 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jun-Hao Deng, Kuan-Wen Lin, Sheng-Chi Chin, Yu-Ching Lee
  • Patent number: 11079669
    Abstract: An extreme ultraviolet (EUV) mask is received. The EUV mask has an EUV pellicle disposed thereover. The EUV pellicle is coupled to the EUV mask at least in part via glue that is disposed on the EUV mask. The EUV pellicle is removed, thereby exposing the glue. A localized glue-removal process is performed by targeting a region of the EUV mask on which the glue is disposed. The localized glue-removal process is performed without affecting other regions of the EUV mask that do not have the glue disposed thereon. The localized glue-removal process may include injecting a cleaning chemical onto the glue and removing a waste chemical produced by the cleaning chemical and the glue. The localized glue-removal process may also include a plasma process that applies plasma to the glue. The localized glue-removal process may further include a laser process that shoots a focused laser beam at the glue.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzu-Ting Chou, Chung-Hsuan Liu, Kuan-Wen Lin, Chi-Lun Lu, Ting-Hao Hsu, Sheng-Chi Chin
  • Publication number: 20210208505
    Abstract: An extreme ultraviolet lithography method is disclosed. In an example, the EUVL method includes forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first mask to the resist layer; performing a second exposure process to image a second pattern of a second sub-region of the first mask to the resist layer; and performing a third exposure process to image a third pattern of a first sub-region of a second mask to the resist layer. The second and third patterns are identical to the first pattern. The first, second and third exposure processes collectively form a latent image of the first pattern on the resist layer.
    Type: Application
    Filed: March 19, 2021
    Publication date: July 8, 2021
    Inventors: Shinn-Sheng Yu, Ching-Fang Yu, Wen-Chuan Wang, Ting-Hao Hsu, Sheng-Chi Chin, Anthony Yen
  • Patent number: 10955746
    Abstract: An extreme ultraviolet lithography method is disclosed. In an example, the EUVL method includes forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first mask to the resist layer; performing a second exposure process to image a second pattern of a second sub-region of the first mask to the resist layer; and performing a third exposure process to image a third pattern of a first sub-region of a second mask to the resist layer. The second and third patterns are identical to the first pattern. The first, second and third exposure processes collectively form a latent image of the first pattern on the resist layer.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shinn-Sheng Yu, Ching-Fang Yu, Wen-Chuan Wang, Ting-Hao Hsu, Sheng-Chi Chin, Anthony Yen
  • Publication number: 20210072196
    Abstract: Methods and systems disclosed herein use acoustic energy to determine a gap between a wafer and an integrated circuit (IC) processing system and/or determine a thickness of a material layer of the wafer during IC processing implemented by the IC processing system. An exemplary method includes emitting acoustic energy through a substrate and a material layer disposed thereover. The substrate is positioned within an IC processing system. The method further includes receiving reflected acoustic energy from a surface of the substrate and a surface of the material layer disposed thereover and converting the reflected acoustic energy into electrical signals. The electrical signals indicate a thickness of the material layer.
    Type: Application
    Filed: November 23, 2020
    Publication date: March 11, 2021
    Inventors: Jun-Hao Deng, Kuan-Wen Lin, Sheng-Chi Chin, Yu-Ching Lee
  • Patent number: 10859908
    Abstract: A method for fabricating a pellicle assembly for a lithography process includes providing a carrier. A membrane layer is fabricated over the carrier. A pellicle frame is attached to the membrane layer. The carrier is then separated from the membrane layer using a release treatment process.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hao Tseng, Sheng-Chi Chin, Yuan-Chih Chu
  • Patent number: 10845342
    Abstract: Methods and systems disclosed herein use acoustic energy to determine a gap between a wafer and an integrated circuit (IC) processing system and/or determine a thickness of a material layer of the wafer during IC processing implemented by the IC processing system. An exemplary method includes emitting acoustic energy through a substrate and a material layer disposed thereover. The substrate is positioned within an IC processing system. The method further includes receiving reflected acoustic energy from a surface of the substrate and a surface of the material layer disposed thereover and converting the reflected acoustic energy into electrical signals. The electrical signals indicate a thickness of the material layer.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Jun-Hao Deng, Kuan-Wen Lin, Sheng-Chi Chin, Yu-Ching Lee
  • Patent number: 10794872
    Abstract: A system and method for determining clearance between a fabrication tool and a workpiece is provided. In an exemplary embodiment, the method includes receiving a substrate within a tool such that a gap is defined there between. A transducer disposed on a bottom surface of the substrate opposite the gap provides an acoustic signal that is conducted through the substrate. The transducer also receives a first echo from a top surface of the substrate that defines the gap and a second echo from a bottom surface of the tool that further defines the gap. A width of the gap is measured based on the first echo and the second echo. In some embodiments, the bottom surface of the tool is a bottom surface of a nozzle, and the nozzle provides a liquid or a gas in the gap while the transducer is receiving the first and second echoes.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jun-Hao Deng, Kuan-Wen Lin, Sheng-Chi Chin, Yu-Ching Lee
  • Patent number: 10691017
    Abstract: Pellicle-mask systems for advanced lithography, such as extreme ultraviolet lithography, are disclosed herein. An exemplary pellicle-mask system includes a mask having an integrated circuit (IC) pattern, a pellicle membrane, and a pellicle frame. The pellicle frame has a first surface attached to the pellicle membrane and a second surface opposite the first surface attached to the mask, such that the IC pattern of the mask is positioned within an enclosed space defined by the mask, the pellicle membrane, and the pellicle frame. A void is defined between the pellicle frame and the mask, where the void is defined by a portion of the second surface of the pellicle membrane not attached to the mask. The void is not in communication with the enclosed space and is not in communication with an exterior space of the pellicle-mask system.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Ching Lee, Ching-Fang Yu, Chun-Hung Lin, Ting-Hao Hsu, Ching-Hsiang Chang, Sheng-Chi Chin
  • Publication number: 20200150523
    Abstract: An extreme ultraviolet (EUV) mask is received. The EUV mask has an EUV pellicle disposed thereover. The EUV pellicle is coupled to the EUV mask at least in part via glue that is disposed on the EUV mask. The EUV pellicle is removed, thereby exposing the glue. A localized glue-removal process is performed by targeting a region of the EUV mask on which the glue is disposed. The localized glue-removal process is performed without affecting other regions of the EUV mask that do not have the glue disposed thereon. The localized glue-removal process may include injecting a cleaning chemical onto the glue and removing a waste chemical produced by the cleaning chemical and the glue. The localized glue-removal process may also include a plasma process that applies plasma to the glue. The localized glue-removal process may further include a laser process that shoots a focused laser beam at the glue.
    Type: Application
    Filed: December 27, 2019
    Publication date: May 14, 2020
    Inventors: Tzu-Ting Chou, Chung-Hsuan Liu, Kuan-Wen Lin, Chi-Lun Lu, Ting-Hao Hsu, Sheng-Chi Chin
  • Patent number: 10520805
    Abstract: An extreme ultraviolet (EUV) mask having a pellicle disposed thereover is received. The EUV pellicle is coupled to the EUV mask at least in part via glue that is disposed on the EUV mask. The EUV pellicle is removed, thereby exposing the glue. A localized glue-removal process is performed by targeting a region of the EUV mask on which the glue is disposed. The localized glue-removal process is performed without affecting other regions of the EUV mask that do not have the glue disposed thereon. The localized glue-removal process may include injecting a cleaning chemical onto the glue and removing a waste chemical produced by the cleaning chemical and the glue. The localized glue-removal process may also include a plasma process that applies plasma to the glue. The localized glue-removal process may further include a laser process that shoots a focused laser beam at the glue.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzu-Ting Chou, Chung-Hsuan Liu, Kuan-Wen Lin, Chi-Lun Lu, Ting-Hao Hsu, Sheng-Chi Chin
  • Publication number: 20190072849
    Abstract: Pellicle-mask systems for advanced lithography, such as extreme ultraviolet lithography, are disclosed herein. An exemplary pellicle-mask system includes a mask having an integrated circuit (IC) pattern, a pellicle membrane, and a pellicle frame. The pellicle frame has a first surface attached to the pellicle membrane and a second surface opposite the first surface attached to the mask, such that the IC pattern of the mask is positioned within an enclosed space defined by the mask, the pellicle membrane, and the pellicle frame. A void is defined between the pellicle frame and the mask, where the void is defined by a portion of the second surface of the pellicle membrane not attached to the mask. The void is not in communication with the enclosed space and is not in communication with an exterior space of the pellicle-mask system.
    Type: Application
    Filed: November 6, 2018
    Publication date: March 7, 2019
    Inventors: Yu-Ching Lee, Ching-Fang Yu, Chun-Hung Lin, Ting-Hao Hsu, Ching-Hsiang Chang, Sheng-Chi Chin
  • Publication number: 20190033720
    Abstract: An extreme ultraviolet lithography method is disclosed. In an example, the EUVL method includes forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first mask to the resist layer; performing a second exposure process to image a second pattern of a second sub-region of the first mask to the resist layer; and performing a third exposure process to image a third pattern of a first sub-region of a second mask to the resist layer. The second and third patterns are identical to the first pattern. The first, second and third exposure processes collectively form a latent image of the first pattern on the resist layer.
    Type: Application
    Filed: January 3, 2018
    Publication date: January 31, 2019
    Inventors: Shinn-Sheng Yu, Ching-Fang Yu, Wen-Chuan Wang, Ting-Hao Hsu, Sheng-Chi Chin, Anthony Yen
  • Publication number: 20180348171
    Abstract: Methods and systems disclosed herein use acoustic energy to determine a gap between a wafer and an integrated circuit (IC) processing system and/or determine a thickness of a material layer of the wafer during IC processing implemented by the IC processing system. An exemplary method includes emitting acoustic energy through a substrate and a material layer disposed thereover. The substrate is positioned within an IC processing system. The method further includes receiving reflected acoustic energy from a surface of the substrate and a surface of the material layer disposed thereover and converting the reflected acoustic energy into electrical signals. The electrical signals indicate a thickness of the material layer.
    Type: Application
    Filed: July 27, 2018
    Publication date: December 6, 2018
    Inventors: Jun-Hao Deng, Kuan-Wen Lin, Sheng-Chi Chin, Yu-Ching Lee
  • Patent number: 10126644
    Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame attached to the pellicle membrane. The pellicle frame has a surface that defines at least one groove. The apparatus further includes a substrate that is in contact with the surface of the pellicle frame such that the grove is positioned between the pellicle frame and the substrate.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: November 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Ching Lee, Ching-Fang Yu, Chun-Hung Lin, Ting-Hao Hsu, Ching-Hsiang Chang, Sheng-Chi Chin
  • Patent number: 10061193
    Abstract: A method includes loading a mask having a defect into a chamber. The defect of the mask is repaired by forming a repair feature in a repair region of the mask. The forming the repair feature includes irradiating the repair region of the mask with a radiation beam. The forming the repair feature further includes while irradiating the repair region, injecting a precursor gas into the chamber to form a first film of the repair feature on the repair region, and while irradiating the repair region, injecting a cleaning gas into the chamber. The cleaning gas reacts with an impurity material in the first film to transform the first film into a first cleaned film.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: August 28, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsun-Chuan Shih, Sheng-Chi Chin, Yuan-Chih Chu, Yueh-Hsun Li
  • Publication number: 20180203347
    Abstract: A method includes loading a mask having a defect into a chamber. The defect of the mask is repaired by forming a repair feature in a repair region of the mask. The forming the repair feature includes irradiating the repair region of the mask with a radiation beam. The forming the repair feature further includes while irradiating the repair region, injecting a precursor gas into the chamber to form a first film of the repair feature on the repair region, and while irradiating the repair region, injecting a cleaning gas into the chamber. The cleaning gas reacts with an impurity material in the first film to transform the first film into a first cleaned film.
    Type: Application
    Filed: March 12, 2018
    Publication date: July 19, 2018
    Inventors: Hsun-Chuan SHIH, Sheng-Chi CHIN, Yuan-Chih CHU, Yueh-Hsun LI
  • Patent number: 9933699
    Abstract: A pellicle is disposed over a lithography mask. An acoustic wave generator is placed over the pellicle. The acoustic wave generator is configured to generate acoustic waves to cause the pellicle to vibrate at a target resonance frequency. A resonance detection tool is configured to detect an actual resonance frequency of the pellicle in response to the acoustic waves. One or more electronic processors are configured to estimate an age condition of the pellicle as a function of a shift of the actual resonance frequency from the target resonance frequency.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: April 3, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Ching Lee, Ching-Fang Yu, Chun-Hung Lin, Sheng-Chi Chin, Ting-Hao Hsu, Mark Chang
  • Publication number: 20180088459
    Abstract: A method for fabricating a pellicle assembly for a lithography process includes providing a carrier. A membrane layer is fabricated over the carrier. A pellicle frame is attached to the membrane layer. The carrier is then separated from the membrane layer using a release treatment process.
    Type: Application
    Filed: December 1, 2017
    Publication date: March 29, 2018
    Inventors: Chun-Hao TSENG, Sheng-Chi CHIN, Yuan-Chih CHU