Patents by Inventor Sheng-Chi Chin

Sheng-Chi Chin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050031966
    Abstract: A method of fabricating a photomask having improved critical dimension (CD) uniformity that meets or exceeds 90 nanometer technology requirements. The method includes the steps of: providing a transparent substrate covered with a layer of opaque material and a layer of photoresist; patterning the layer of photoresist to expose an area of the layer of opaque material that has a shape that follows a contour of a main pattern area to be defined by the layer of opaque material; removing the exposed area to define the layer of opaque material into the main pattern area and an area that surrounds the main pattern area; removing the patterned layer of photoresist; and removing the surrounding area of the layer of opaque material.
    Type: Application
    Filed: August 8, 2003
    Publication date: February 10, 2005
    Inventors: Wen-Chuan Wang, Shih-Ming Chang, Chih-Chen Chin, Chi-Lun Lu, Sheng-Chi Chin, Hung-Chang Hsieh
  • Publication number: 20040265704
    Abstract: A multiple-exposure defect elimination process for semiconductor devices being fabricated on semiconductor wafers using photomask parts, including one mask part that is defective, is disclosed. A semiconductor wafer is exposed to a first mask part that is at least partially defective, and then is exposed to a second mask part corresponding to the first mask part but that is at least substantially free from defects or with defects at different locations. The mask parts may be on the same or different photomasks, and have the same layout for a semiconductor device that is being fabricated. Furthermore, the semiconductor wafer may be exposed to the second or other additional mask parts one or more additional times.
    Type: Application
    Filed: June 26, 2003
    Publication date: December 30, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Ming Chang, Chih-Cheng Chin, Wen-Chuan Wang, Chi-Lun Lu, Sheng-Chi Chin, Chin-Hsiang Lin
  • Patent number: 6830853
    Abstract: A method of forming photomasks is described which provides good critical dimension control for critical pattern elements and provides good throughput and low defect levels for etching relatively large areas of opaque material. The pattern is first modified to form a frame around the pattern elements which require good critical dimension control. The opaque material, such as chrome, in this frame is then etched away using dry anisotropic etching. The dry anisotropic etching provides good critical dimension control. The remainder of the opaque material to be removed is then etched away using wet isotropic etching. The wet isotropic etching provides good defect control in this region of the mask and good throughput. This method provides good critical dimension control at the edges of the pattern elements, good throughput in mask fabrication, and good defect level control in removing the relatively large areas of opaque material which do not affect critical dimension control.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: December 14, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: San-De Tzu, Sheng-Chi Chin, Chung-Hsing Chang, Hsin-Chang Li
  • Publication number: 20040225488
    Abstract: A method and system is disclosed for examining mask pattern fidelity. First, a mask picture is generated from a first mask with a first OPC model applied to a mask design thereon. The mask picture is then converted into a mask based simulation file. A first simulation is conducted under a first set of predetermined lithography processing conditions using the converted simulation file to generate one or more files of a first set representing wafer photo resist profile thereof. On the other hand, a mask design in a database mask file is identified which was used for generating the first mask. The first OPC model is applied to the mask design in the database mask file. A second simulation is then conducted under the first set of predetermined lithography processing conditions using the OPCed mask design to generate one or more files of a second set representing wafer photo resist profile thereof. The first and second sets of files are then evaluated together for the purpose of inspecting mask fidelity.
    Type: Application
    Filed: September 19, 2003
    Publication date: November 11, 2004
    Inventors: Wen-Chuan Wang, Shih-Ming Chang, Chih-Cheng Chin, Chi-Lun Lu, Sheng-Chi Chin, Hung-Chang Hsieh
  • Patent number: 6599665
    Abstract: A mask used to image circuit patterns onto a semiconductor wafer exhibits improved uniformity of critical feature dimensions. A pattern of dummy features is formed around the outer periphery of the main pattern during manufacture of the mask. The presence of the dummy field eliminates loading of the etch rate at the marginal areas of the main pattern, thereby assuring that all of the features in the main pattern field are etched at substantially the same rate. By using differing radiation dosages to expose the photoresist employed to form the main pattern and dummy patterns, a thickness of the photoresist remains over the dummy field pattern after development of the photoresist. This remaining photoresist has a thickness sufficient to prevent subsequent etching of the underlying metal which would otherwise leave features in the metal layer that would be imaged onto the wafer.
    Type: Grant
    Filed: October 10, 2000
    Date of Patent: July 29, 2003
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shy-Jay Lin, Sheng-Chi Chin
  • Patent number: 6428938
    Abstract: An improved phase-shift photomask and method of fabrication are described. The method for making this phase-shift mask involves depositing an opaque film, such as chromium (Cr), on a transparent plate, such as SiO2 (quartz plate). An electron beam photoresist layer is deposited on the Cr film and is partially exposed in regions A and completely exposed in closely spaced alternate regions B by an electron beam. The exposed photoresist is then developed. The Cr film is etched in regions B while the remaining resist in regions A protect the Cr from etching. The e-bean resist is plasma etched back to remove the resist over regions A and then the quartz plate in regions B is recessed to a depth d by plasma etching while the Cr protects the quartz in regions A from etching. The recess is etched to a depth to provide an optical path difference between A and B of ½ wavelength (180°) when UV light is transmitted through the mask to expose resist on a product substrate.
    Type: Grant
    Filed: June 19, 2000
    Date of Patent: August 6, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chin-Hsiang Lin, Shy-Jay Lin, Sheng-Chi Chin, Wei-Zen Chou