Patents by Inventor Sheng Chou

Sheng Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240385610
    Abstract: A computing system includes one or more electronic components, a first programmable device, and a baseboard management controller (BMC). The first programmable device is communicatively coupled to a first subset of the one or more electronic components. The first programmable device is configured to detect event activities associated with the first subset and to store the event activities as stored first event data. The BMC includes a system event log. The BMC is communicatively coupled to the first programmable device. The BMC is configured to receive the stored first event data and to write the stored first event data in the system event log.
    Type: Application
    Filed: May 18, 2023
    Publication date: November 21, 2024
    Inventors: Le-Sheng CHOU, Sz-Chin SHIH, Shuen-Hung WANG, Hsien-Chang LI
  • Patent number: 12148685
    Abstract: A redistribution layer structure is provided. The redistribution layer structure includes a first metal layer and a first dielectric layer disposed on the first metal layer. A range of a difference between a coefficient of thermal expansion of the first dielectric layer and a coefficient of thermal expansion of the first metal layer is 0% to 70% of the coefficient of thermal expansion of the first dielectric layer.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: November 19, 2024
    Assignee: Innolux Corporation
    Inventors: Hung-Sheng Chou, Wen-Hsiang Liao, Kuo-Jung Fan, Heng-Shen Yeh, Cheng-Chi Wang
  • Publication number: 20240373166
    Abstract: The present invention discloses a glass diaphragm having a functional layer which is selected from one of the following group or the combination thereof: explosion-proof layer, decorative layer, waterproof layer, and anti-reflection layer. The anti-explosion layer is made of PU, PVB, PC, PET or PMMA, the decorative layer contains ink materials, and the anti-reflection layer includes porous or raised structures formed by nanometer materials. The functional layer is formed by coating, spraying, pasting, ink jetting, coating.
    Type: Application
    Filed: July 1, 2023
    Publication date: November 7, 2024
    Inventors: Yi-Feng WEI, Kwun-Kit CHAN, Yao-Sheng CHOU
  • Publication number: 20240367002
    Abstract: The present invention discloses a sports and health cloud analysis system including a cloud server with an intelligent analysis module, a big data database is coupled to the cloud server, a wearable sensing module is coupled to a mobile device for collecting at least heart sound, ECG, lung sounds, blood pressure, blood glucose level and blood oxygen saturation level information; an insole-type sensing module is used to collect at least foot information, which is connected to the mobile device. The sensing module performs at least one of exercise sensing, foot, exercise, ankle exercise, knee exercise, hand exercise. The collected information is analyzed by an intelligent analysis module to obtain data for evaluating the health status and exercise intensity.
    Type: Application
    Filed: June 16, 2023
    Publication date: November 7, 2024
    Inventors: Yao-Sheng CHOU, Chung-Yuan WU, Yen-Han CHOU
  • Publication number: 20240363688
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a heat transfer layer disposed over a substrate, a channel material layer, a gate structure and source and drain terminals. The channel material layer has a first surface and a second surface opposite to the first surface, and the channel material layer is disposed on the heat transfer layer with the first surface in contact with the heat transfer layer. The gate structure is disposed above the channel material layer. The source and drain terminals are in contact with the channel material layer and located at two opposite sides of the gate structure.
    Type: Application
    Filed: July 4, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tse Hung, Ang-Sheng Chou, Hung-Li Chiang, Tzu-Chiang Chen, Chao-Ching Cheng
  • Publication number: 20240324714
    Abstract: An insole with wireless charging system includes a pressure sensing layer arranged on the insole, a sensing device is formed in the insole to detect speed, distance, direction, acceleration, angular orientation or any combination thereof. An inductive coil is formed in the insole for wireless charging a battery.
    Type: Application
    Filed: June 10, 2024
    Publication date: October 3, 2024
    Inventors: Yao-Sheng Chou, Chung-Yuan Wu, Hsiao-Yi Lin
  • Publication number: 20240321445
    Abstract: A combined smart sensing pad monitoring system, which includes a planar sensing pad array having a plurality of pressure sensing pads, each of them is a wireless pressure sensing device configured to sense the pressure data of different areas of the planar sensing pad array, an external electronic computing device communicatively connected to the planar sensing pad array to receive the pressure data detected by the plurality of pressure sensing pads. The external electronic computing device combines the pressure data detected by the plurality of pressure sensing pads with the positioning information associated with individual pressure sensing pads to form a pressure distribution. The external electronic computing device monitors the pressure distribution and duration to determine whether to issue a warning.
    Type: Application
    Filed: January 10, 2024
    Publication date: September 26, 2024
    Inventors: Yao-Sheng CHOU, Hsiao-Yi LIN, Yen-Han CHOU
  • Patent number: 12062696
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a heat transfer layer disposed over a substrate, a channel material layer, a gate structure and source and drain terminals. The channel material layer has a first surface and a second surface opposite to the first surface, and the channel material layer is disposed on the heat transfer layer with the first surface in contact with the heat transfer layer. The gate structure is disposed above the channel material layer. The source and drain terminals are in contact with the channel material layer and located at two opposite sides of the gate structure.
    Type: Grant
    Filed: July 14, 2023
    Date of Patent: August 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tse Hung, Ang-Sheng Chou, Hung-Li Chiang, Tzu-Chiang Chen, Chao-Ching Cheng
  • Patent number: 12052535
    Abstract: A passive sounding device integrated into a flat panel display includes a glass diaphragm having a first surface for forming a light-emitting array of the flat-panel display thereon, a suspension edge, and a frame, wherein the glass diaphragm is tightly sealed with the frame through the suspension edge to form an airtight space in the frame, and the glass diaphragm vibrates and emits sound in response to the pressure of the sound waves generated by an active sounding device.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: July 30, 2024
    Assignee: Glass Acoustic Innovations Co., Ltd.
    Inventors: Yao-Sheng Chou, Hsiao-Yi Lin, Yi-Feng Wei
  • Publication number: 20240231640
    Abstract: A memory operation method, comprising: when a first super block of a memory device is a open block (or in programming state), obtaining a first read count of one of a plurality of first memory blocks in the first super block, wherein the first read count is a number of times that data of one of the first memory blocks is read out; determining whether the first read count is larger than a first threshold; and when the first read count is larger than the first threshold, moving a part of the data in the first super block to a safe area in the memory device, wherein the part of the data comprises data in the first memory block.
    Type: Application
    Filed: June 6, 2023
    Publication date: July 11, 2024
    Inventors: Po-Sheng CHOU, Hsiang-Yu HUANG, Yan-Wen WANG
  • Patent number: 12029277
    Abstract: An insole with embedded sensing system includes a pressure sensing layer arranged on the insole, an infrared sensing layer arranged inside the insole, and a sensing module installed inside an arch pad integrated with the insole. The sensing module is electrically coupled with the pressure sensing layer and the infrared sensing layer for receiving and processing detected electronic signals.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: July 9, 2024
    Assignee: Decentralized Biotechnology Intelligence Co., Ltd.
    Inventors: Yao-Sheng Chou, Pai-Ching Wei
  • Patent number: 12028668
    Abstract: A sound wave transducer is provided. The sound wave transducer includes a first board, a spacer layer and a second board over the first board and the spacer layer. The first board includes a carrier, a first substrate layer and a first metal layer. The carrier has a first opening formed in a central region. The first substrate layer is disposed on the carrier and over the first opening. The first metal layer is disposed on the first substrate layer. The spacer layer is disposed on the first board and surrounds the central region. The second board includes a second substrate layer, a second metal layer disposed on the spacer layer, and a plurality of second openings penetrating through the second substrate layer and the second metal layer.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: July 2, 2024
    Assignee: GLASS ACOUSTIC INNOVATIONS TECHNOLOGY CO., LTD.
    Inventors: Hsiao-Yi Lin, Kwun Kit Chan, Yi Feng Wei, Yao-Sheng Chou
  • Publication number: 20240213246
    Abstract: A semiconductor device includes a gate layer, a channel material layer, a first dielectric layer and source/drain terminals. The gate layer is disposed over a substrate. The channel material layer is disposed over the gate layer, where a material of the channel material layer includes a first low dimensional material. The first dielectric layer is between the gate layer and the channel material layer. The source/drain terminals are in contact with the channel material layer, where the channel material layer is at least partially disposed between the source/drain terminals and over the gate layer, and the gate layer is disposed between the substrate and the source/drain terminals.
    Type: Application
    Filed: March 6, 2024
    Publication date: June 27, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tse Hung, Ang-Sheng Chou, Hung-Li Chiang, Tzu-Chiang Chen, Chao-Ching Cheng
  • Publication number: 20240188922
    Abstract: A multi-dimensional artificial intelligence auscultation device includes multiple heart sound sensors configured to place on different heart sound auscultation positions of the body to be monitored for simultaneously capturing heart sound signals corresponding to the different heart sound auscultation positions, and a processing unit is electrically coupled to the heart sound sensors to perform pre-processing such as filtering, signal amplification and digitization on the collected heart sound signals. The pre-processed heart sound signals are analyzed and cross-compared by an external computing device to obtain the correlations between individual heart sound signals of the multiple heart sound signals.
    Type: Application
    Filed: October 12, 2023
    Publication date: June 13, 2024
    Inventors: Yao-Sheng Chou, Wei-Sheng Su, Hsiao-Yi Lin
  • Publication number: 20240188930
    Abstract: The present invention discloses an adhesive ultrasonic sensing device including a flexible substrate for attaching to a part of a body; a first electrode layer is configured on the flexible substrate; an ultrasonic sensor array is configured on the first electrode layer. A second electrode layer is disposed on the ultrasonic sensor array; and a thin film transistor layer, is configured on the second electrode layer. The ultrasonic sensor array emits ultrasonic waves to the part, and receives reflected ultrasonic waves from the part.
    Type: Application
    Filed: September 20, 2023
    Publication date: June 13, 2024
    Inventors: Yao-Sheng Chou, Wei-Sheng Su, Hsiao-Yi Lin
  • Publication number: 20240188836
    Abstract: An integrated sensing device for heart sounds and electrocardiographic signals, which includes a plurality of integrated sensing units for heart sounds and electrocardiographic signals, each sensing unit having a flexible base with upper and lower surfaces, and a plurality of electrodes been arranged on the lower surface of the flexible base, a piezoelectric layer arranged on the upper surface of the flexible base, a piezoelectric electrode formed on the piezoelectric layer, a metal buckle passing through the flexible base and the piezoelectric layer, as an electrical connection to the plurality of electrodes. The pluralities of electrodes are used for sensing body electrocardiogram signals, and one of the plurality of electrodes together with the piezoelectric electrode are used for sensing body heart sound signals. A system circuit board is used to filter, to amplify, and to digitalize collected multiple heart sounds and multiple ECG signals.
    Type: Application
    Filed: November 12, 2023
    Publication date: June 13, 2024
    Inventors: Yao-Sheng Chou, Wei-Sheng Su, Hsiao-Yi Lin
  • Publication number: 20240188923
    Abstract: A wearable stethoscope includes a clothing body, a sound sensor configured to collect heart sound signals of a user, the sound sensor having a diaphragm, a piezoelectric sensor, and a circuit board. The circuit board is electrically connected to the sound sensor and the piezoelectric sensor to preprocess the collected heart sound signals. The sound sensor is integrated with the clothing body.
    Type: Application
    Filed: March 30, 2023
    Publication date: June 13, 2024
    Inventors: Yao-Sheng CHOU, Wei-Sheng SU, Hsiao-Yi LIN
  • Patent number: 12008258
    Abstract: A solution for deteriorated non-volatile memory is shown. When determining that raw data read from the non-volatile memory is undesirable data, the controller updates a deterioration table to record a deteriorated logical address of the raw data that is the undesirable data. In response to a read request that a host issues to read the non-volatile memory for data of the deteriorated logical address, the controller obtains the deteriorated logical address from the deterioration table and informs the host that deterioration has happened at the deteriorated logical address.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: June 11, 2024
    Assignee: SILICON MOTION, INC.
    Inventors: Yu-Hao Chang, Yu-Han Hsiao, Po-Sheng Chou
  • Patent number: 11984353
    Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Jhy-Jyi Sze
  • Publication number: 20240153987
    Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 9, 2024
    Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Ching-Chun Wang