Patents by Inventor Sheng Chou

Sheng Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11749718
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a heat transfer layer disposed over a substrate, a channel material layer, a gate structure and source and drain terminals. The channel material layer has a first surface and a second surface opposite to the first surface, and the channel material layer is disposed on the heat transfer layer with the first surface in contact with the heat transfer layer. The gate structure is disposed above the channel material layer. The source and drain terminals are in contact with the channel material layer and located at two opposite sides of the gate structure.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tse Hung, Ang-Sheng Chou, Hung-Li Chiang, Tzu-Chiang Chen, Chao-Ching Cheng
  • Publication number: 20230266906
    Abstract: A solution for deteriorated non-volatile memory is shown. When a controller determines that raw data read from the non-volatile memory is undesirable data, the controller performs safety moving of valid data of an erasure unit that contains the raw data to safely move the valid data of the erasure unit, wherein the erasure unit is a high-risk block, and the raw data in the non-volatile memory is regarded as being in a deteriorated physical address. Prior to being moved in the safety moving, the raw data is changed so that it is different from the undesirable data. In an exemplary embodiment, the undesirable data is all-1's data or all-0's data.
    Type: Application
    Filed: June 8, 2022
    Publication date: August 24, 2023
    Inventors: Yu-Hao CHANG, Yu-Han HSIAO, Po-Sheng CHOU
  • Publication number: 20230267038
    Abstract: A solution for deteriorated non-volatile memory is shown. When determining that raw data read from the non-volatile memory is undesirable data, the controller updates a deterioration table to record a deteriorated logical address of the raw data that is the undesirable data. When performing garbage collection from a source block associated with the deteriorated logical address to a destination block and determining that the deteriorated logical address is listed in the deterioration table, the controller invalidates target data stored in the source block and mapped to the deteriorated logical address, without moving the target data from the source block to the destination block in the garbage collection.
    Type: Application
    Filed: June 8, 2022
    Publication date: August 24, 2023
    Inventors: Yu-Hao CHANG, Yu-Han HSIAO, Po-Sheng CHOU
  • Publication number: 20230266912
    Abstract: A solution for deteriorated non-volatile memory is shown. When determining that raw data read from the non-volatile memory is undesirable data, the controller updates a deterioration table to record a deteriorated logical address of the raw data that is the undesirable data. In response to a read request that a host issues to read the non-volatile memory for data of the deteriorated logical address, the controller obtains the deteriorated logical address from the deterioration table and informs the host that deterioration has happened at the deteriorated logical address.
    Type: Application
    Filed: June 8, 2022
    Publication date: August 24, 2023
    Inventors: Yu-Hao CHANG, Yu-Han HSIAO, Po-Sheng CHOU
  • Publication number: 20230218261
    Abstract: The present invention discloses a smart noise reduction device including a control device; an audio waveform pattern recognizer coupled to the control device for identifying an audio mixed signal including a regularity signal and a non-regularity signal; an audio waveform pattern database coupled to the control device, including at least one audio type, each having a plurality of preset second regularity signals; and an audio filter coupled to the control device to obtain the regularity signal.
    Type: Application
    Filed: October 15, 2022
    Publication date: July 13, 2023
    Inventors: Yao-Sheng Chou, Hsiao-Yi Lin, Yen-Han Chou
  • Publication number: 20230223033
    Abstract: The present invention discloses a method of noise reduction for an intelligent network communication, which includes the following steps: first, receiving a local sound message through a sound receiver of a communication device at the transmitting end. Next, a voice recognizer is used to identify the voice characteristics of the speaker; then, it is determined from a voice database whether there is a corresponding or similar voice characteristic of the speaker recognized by the voice recognizer. Finally, filtering other signals other than the voice characteristic signal of the speaker through a sound filter to obtain the original sound emitted by the speaker.
    Type: Application
    Filed: October 15, 2022
    Publication date: July 13, 2023
    Inventors: Yao-Sheng Chou, Hsiao-Yi Lin, Yen-Han Chou
  • Patent number: 11693814
    Abstract: A system and device for expanding accessible memory of a processor is provided. An interposer is coupled to the processor and a memory module. The interposer is coupled to a first connection and a second connection. The interposer includes a memory controller circuit. The memory controller circuit receives signals from the processor, using the first connection, and transmits the received signals to the memory module, using the second connection. The interposer expands memory access without an unnecessary second processor.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: July 4, 2023
    Assignee: QUANTA COMPUTER INC.
    Inventors: Le-Sheng Chou, Sz-Chin Shih
  • Publication number: 20230140164
    Abstract: A computing system is provided. The computing system includes a central processing unit (CPU), a baseboard management controller (BMC), and a boot non-volatile memory. The BMC selects a boot partition in the computing system. The boot non-volatile memory stores at least two boot partitions as a primary boot area including a basic input/output system (BIOS) image and a secondary boot area including a BMC image. The BMC switches between the secondary boot area to boot the BMC and the primary boot area to boot the BIOS. Only one of the primary boot area or the secondary boot area is accessible when the BIOS is booting or when the BMC is booting.
    Type: Application
    Filed: November 2, 2021
    Publication date: May 4, 2023
    Inventor: Chih-Sheng CHOU
  • Patent number: 11622199
    Abstract: A hybrid diaphragm structure is provided. The hybrid diaphragm structure includes a substrate, a first diaphragm disposed in a central region of the substrate, a first coil structure disposed over the first diaphragm, a first groove separating the first diaphragm and the first coil structure from the substrate, and a first bridge structure coupling the first diaphragm to the substrate. The first diaphragm and the substrate include a same material.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: April 4, 2023
    Assignee: GLASS ACOUSTIC INNOVATIONS TECHNOLOGY CO., LTD.
    Inventors: Yao-Sheng Chou, Kwun Kit Chan, Yi Feng Wei, Hsiao-Yi Lin
  • Patent number: 11604530
    Abstract: The present invention provides a novel pixel array with touch component integration, the structure includes pluralities of the pixels, arranged in an array with a gap between the horizontal space. Two touch electrode layers are arranged in the gap which are alternately with the pixels, thereby the spatial integration efficiency could be improved by integrating touch sensing electrode layers within the display pixels.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: March 14, 2023
    Assignee: Decentralized Biotechnology Intelligence Co., Ltd.
    Inventor: Yao-Sheng Chou
  • Publication number: 20230054536
    Abstract: A passive sounding device integrated into a flat panel display includes a glass diaphragm having a first surface for forming a light-emitting array of the flat-panel display thereon, a suspension edge, and a frame, wherein the glass diaphragm is tightly sealed with the frame through the suspension edge to form an airtight space in the frame, and the glass diaphragm vibrates and emits sound in response to the pressure of the sound waves generated by an active sounding device.
    Type: Application
    Filed: August 16, 2022
    Publication date: February 23, 2023
    Inventors: Yao-Sheng Chou, Hsiao-Yi Lin, Yi-Feng Wei
  • Publication number: 20230053470
    Abstract: An active sounding device integrated into a flat panel display includes a glass diaphragm having a first surface on which a light emitting array and a touch panel are formed, a plurality of planar voice coils arranged on the second surface of the glass diaphragm opposite to the first surface, and a magnet assembly arranged below the plurality of planar voice coils, wherein the plurality of planar voice coils are electromagnetically coupled to the magnet assembly for converting received electrical signals into vibration signals of the glass diaphragm and making the flat panel display emitting sound.
    Type: Application
    Filed: August 16, 2022
    Publication date: February 23, 2023
    Inventors: Yao-Sheng Chou, Hsiao-Yi Lin, Yi-Feng Wei
  • Publication number: 20230032620
    Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.
    Type: Application
    Filed: March 21, 2022
    Publication date: February 2, 2023
    Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Ching-Chun Wang
  • Publication number: 20220409130
    Abstract: A wearable stethoscope includes a sound sensing device for collecting heart sound signals of the body, an electrocardiogram sensing device for collecting electrocardiogram signals of the body, a processing unit, powered by a power source, coupled to the sound sensing device and the electrocardiogram sensing device to perform data preprocessing on the above-mentioned signals to remove background noise. An external electronic computing device is set up to analyze and process the fed pre-processed ECG signal and heart sound signal, perform feature extraction in combination with the user's physiological parameters and medical records to obtain related feature vectors, input the feature vectors into a screening model, obtain an evaluation value and give corresponding suggestions. After screening, users can upload the verification results to the cloud database to expand the existing training samples for further optimizing the parameters of the screening model.
    Type: Application
    Filed: November 1, 2021
    Publication date: December 29, 2022
    Inventors: Yao-Sheng Chou, YEN-HAN CHOU
  • Publication number: 20220360876
    Abstract: A sound wave transducer is provided. The sound wave transducer includes a first board, a spacer layer and a second board over the first board and the spacer layer. The first board includes a carrier, a first substrate layer and a first metal layer. The carrier has a first opening formed in a central region. The first substrate layer is disposed on the carrier and over the first opening. The first metal layer is disposed on the first substrate layer. The spacer layer is disposed on the first board and surrounds the central region. The second board includes a second substrate layer, a second metal layer disposed on the spacer layer, and a plurality of second openings penetrating through the second substrate layer and the second metal layer.
    Type: Application
    Filed: May 6, 2022
    Publication date: November 10, 2022
    Inventors: HSIAO-YI LIN, KWUN KIT CHAN, YI FENG WEI, YAO-SHENG CHOU
  • Publication number: 20220300965
    Abstract: A smart transaction device with multiple fingerprint recognition includes a device body having a first surface and a second surface on the opposite side, a plurality of fingerprint sensing devices being respectively arranged on the first surface and the second surface to individually sense the fingerprints of different fingers of a user and store them in the memory as comparison data.
    Type: Application
    Filed: November 1, 2021
    Publication date: September 22, 2022
    Inventors: Yen-Han Chou, Yao-Sheng Chou
  • Publication number: 20220301364
    Abstract: The present invention provides a driver and passenger behavior information system which includes a sensing device to detect a driving behavior signal, wherein the sensing device is set at the vehicle control associated apparatus for controlling the vehicle and sensing the driving behavior signal by the sensing device, a driving behavior record device is coupled to the sensing device to store the sensing signals.
    Type: Application
    Filed: March 16, 2022
    Publication date: September 22, 2022
    Inventors: Yen-Han CHOU, Yao-Sheng CHOU
  • Publication number: 20220300590
    Abstract: A method for protecting application programs of electronic computing devices, which includes arranging a fingerprint detection device at least partially overlapped on the display screen of the electronic computing device, setting a verification area on the display screen to lock or unlock the software applications or files framed by the verification area and to protect the framed software applications or files from unauthorized retrieving.
    Type: Application
    Filed: November 1, 2021
    Publication date: September 22, 2022
    Inventors: Yen-Han Chou, Yao-Sheng Chou
  • Publication number: 20220285345
    Abstract: A semiconductor device includes a gate layer, a channel material layer, a first dielectric layer and source/drain terminals. The gate layer is disposed over a substrate. The channel material layer is disposed over the gate layer, where a material of the channel material layer includes a first low dimensional material. The first dielectric layer is between the gate layer and the channel material layer. The source/drain terminals are in contact with the channel material layer, where the channel material layer is at least partially disposed between the source/drain terminals and over the gate layer, and the gate layer is disposed between the substrate and the source/drain terminals.
    Type: Application
    Filed: June 23, 2021
    Publication date: September 8, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tse Hung, Ang-Sheng Chou, Hung-Li Chiang, Tzu-Chiang Chen, Chao-Ching Cheng
  • Publication number: 20220285495
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a heat transfer layer disposed over a substrate, a channel material layer, a gate structure and source and drain terminals. The channel material layer has a first surface and a second surface opposite to the first surface, and the channel material layer is disposed on the heat transfer layer with the first surface in contact with the heat transfer layer. The gate structure is disposed above the channel material layer. The source and drain terminals are in contact with the channel material layer and located at two opposite sides of the gate structure.
    Type: Application
    Filed: June 18, 2021
    Publication date: September 8, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tse Hung, Ang-Sheng Chou, Hung-Li Chiang, Tzu-Chiang Chen, Chao-Ching Cheng