Patents by Inventor Sheng Chu

Sheng Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250131892
    Abstract: A display device has a backlight module with a plurality of light-emitting units. The light-emitting units are divided into a plurality of groups, and each group constitutes a lighting region. A backlight compensation method includes performing a local dimming process according to a gamma value of a display device by a backlight module; obtaining an area peak luminance of each lighting area; selecting one of the lighting regions as a selected region; obtaining a regional average luminance value based on the area peak luminance of the selected region and the area peak luminance of other lighting regions adjacent to the selected region; obtaining a luminance adjustment ratio based on a partial peak ratio corresponding to the regional average luminance value; obtaining a compensation luminance value based on the luminance peak value and the luminance adjustment ratio; and adjusting the luminance of the selected region based on the compensation luminance value.
    Type: Application
    Filed: December 27, 2024
    Publication date: April 24, 2025
    Inventors: PO-KUN CHEN, CHIA SHENG CHU, CHIA CHIA LI, REN-WEI HUANG
  • Patent number: 12276236
    Abstract: The provided is energy storage method and device for biomass cascade pyrolysis coupled with new energy power generation. The key point of the technical solution is that, with inexpensive, clean and safe biomass as energy storage medium, the redundant unstable electric energy is converted by a cascade pyrolysis energy storage system into an easy-to-store liquid and solid chemical energy in biomass pyrolytic products, and based on use requirements, can be further converted into clean fuels for power generation or exported renewable chemicals, so as to realize continuous stable output of the new energy power generation systems. Furthermore, the cascade pyrolysis energy storage system can, based on the principle of “energy level matching”, fully recover and utilize the electric energy, high-temperature heat energy and low-temperature heat energy generated in pyrolysis processes, thereby maximizing the energy utilization efficiency of the system.
    Type: Grant
    Filed: November 25, 2024
    Date of Patent: April 15, 2025
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Huiyan Zhang, Yinhai Su, Bo Peng, Sheng Chu, Yujie Tao, Qi Cao, Rui Xiao
  • Publication number: 20250095406
    Abstract: This document describes systems and techniques that enable continuous personalization of face authentication. In aspects, an authentication system associated with a network includes an authentication manager. The authentication manager receives an embedding representing image data associated with a user's face. The authentication manager generates a confidence score based on the embedding. Further, the authentication manager updates previously enrolled embeddings with the embedding based on the confidence score, the embedding meeting a clustering confidence threshold. Through such a technique, the authentication manager can alter the previously enrolled embeddings by which a future embedding is used to authenticate the user's face. By so doing, the techniques may provide more-accurate and successful user authentication over time.
    Type: Application
    Filed: December 5, 2024
    Publication date: March 20, 2025
    Applicant: Google LLC
    Inventors: Cem Kemal Hamami, Philip Andrew Mansfield, Samuel Paradis, Michael Williams, Wen-Sheng Chu
  • Publication number: 20250084805
    Abstract: The provided is energy storage method and device for biomass cascade pyrolysis coupled with new energy power generation. The key point of the technical solution is that, with inexpensive, clean and safe biomass as energy storage medium, the redundant unstable electric energy is converted by a cascade pyrolysis energy storage system into an easy-to-store liquid and solid chemical energy in biomass pyrolytic products, and based on use requirements, can be further converted into clean fuels for power generation or exported renewable chemicals, so as to realize continuous stable output of the new energy power generation systems. Furthermore, the cascade pyrolysis energy storage system can, based on the principle of “energy level matching”, fully recover and utilize the electric energy, high-temperature heat energy and low-temperature heat energy generated in pyrolysis processes, thereby maximizing the energy utilization efficiency of the system.
    Type: Application
    Filed: November 25, 2024
    Publication date: March 13, 2025
    Applicant: SOUTHEAST UNIVERSITY
    Inventors: Huiyan ZHANG, Yinhai SU, Bo PENG, Sheng CHU, Yujie TAO, Qi CAO, Rui XIAO
  • Publication number: 20250037353
    Abstract: Systems and methods for training a generative neural radiance field model can include geometric regularization. Geometric regularization can involve the utilization of reference geometry data and/or an output of a surface prediction model. The geometry regularization can train the generative neural radiance field model to mitigate artifact generation by limiting a distribution considered for color value prediction and density value prediction to a range associated with a realistic geometry range.
    Type: Application
    Filed: January 13, 2022
    Publication date: January 30, 2025
    Inventors: Wen-Sheng Chu, Dmitry Lagun, Ioannis Daras, Abhishek Kumar
  • Publication number: 20250029424
    Abstract: A method includes obtaining dual-pixel image data that represents an object and includes a first sub-image and a second sub-image, and generating (i) a first feature map based on the first sub-image and (ii) a second feature map based on the second sub-image. The method also includes generating a correlation volume by determining, for each respective offset of a plurality of offsets between the first feature map and the second feature map, pixel-wise similarities between (i) the first feature map and (ii) the second feature map offset from the first feature map by the respective offset. The method further includes determining, by an anti-spoofing model and based on the correlation volume, a spoofing value indicative of a likelihood that the object represented by the dual-pixel image data is being spoofed.
    Type: Application
    Filed: April 1, 2022
    Publication date: January 23, 2025
    Inventors: Siyuan Qiao, Wen-Sheng Chu
  • Publication number: 20250027227
    Abstract: Provided are a silicon carbide crystal growth device and a quality control method. The device includes: an annealing unit, a crystal growth unit, an atmosphere control unit, and a transport system; the atmosphere control unit provides a gas environment with low water, oxygen and nitrogen; the transport system transports a plurality of target objects after high-temperature purification by the annealing unit to the atmosphere control unit; after assembling silicon carbide seed crystal and silicon carbide powder in a graphite crucible and covering with thermal insulation material to form a container inside the atmosphere control unit, the transport system transports the container to the crystal growth unit. The method uses a weighing system in a chamber of the crystal growth unit to detect a weight change of silicon carbide seed crystal and silicon carbide powder during a crystal growth process through a plurality of weight sensors of the weighing system.
    Type: Application
    Filed: July 20, 2023
    Publication date: January 23, 2025
    Inventors: Yun-Fu Chen, Wei-Tse Hsu, Min-Sheng Chu, Chien-Li Yang, Tsu-Hsiang Lin, Yuan-Hong Huang
  • Patent number: 12183117
    Abstract: A method includes receiving data indicative of an image of a face of an unknown user of the computing device while the computing device is in a reduced access mode locked state. The method also includes determining whether the unknown user is the known user by at least comparing the image of the face of the unknown user to one or more images of a plurality of images of a face of a known user of the computing device. The method further includes setting the computing device to an increased access mode in response to determining that the unknown user is the known user.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: December 31, 2024
    Assignee: Google LLC
    Inventors: Cem Kemal Hamami, Joseph Edwin Johnson, Jr., Kuntal Sengupta, Piotr Kulaga, Wen-Sheng Chu, Zachary Iqbal
  • Patent number: 12154939
    Abstract: The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: November 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Sheng Chu, Dun-Nian Yaung, Yu-Cheng Tsai, Meng-Hsien Lin, Ching-Chung Su, Jen-Cheng Liu, Wen-De Wang, Guan-Hua Chen
  • Publication number: 20240387613
    Abstract: The present disclosure, in some embodiments, relates to a capacitor structure. The capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A lower electrode is arranged along sidewalls and an upper surface of the lower dielectric structure, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is arranged along outermost sidewalls of the upper electrode. The spacer includes a first upper surface arranged along a first side of the upper electrode and a second upper surface arranged along an opposing second side of the upper electrode. The first upper surface has a different width than the second upper surface.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 21, 2024
    Inventors: Ching-Sheng Chu, Dun-Nian Yaung, Yu-Cheng Tsai, Meng-Hsien Lin, Ching-Chung Su, Jen-Cheng Liu, Wen-De Wang, Guan-Hua Chen
  • Patent number: 12132039
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first dielectric structure having first inner sidewalls over an interlayer dielectric (ILD) structure. A second dielectric structure is over the first dielectric structure, where the first inner sidewalls are between second inner sidewalls of the second dielectric structure. A sidewall barrier structure is over the first dielectric structure and extends vertically along the second inner sidewalls. A lower bumping structure is between the second inner sidewalls and extends vertically along the first inner sidewalls and vertically along third inner sidewalls of the sidewall barrier structure. An upper bumping structure is over both the lower bumping structure and the sidewall barrier structure and between the second inner sidewalls, where an uppermost point of the upper bumping structure is at or below an uppermost point of the second dielectric structure.
    Type: Grant
    Filed: June 9, 2023
    Date of Patent: October 29, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Sheng Chu, Chern-Yow Hsu
  • Patent number: 12087826
    Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes the following operations. A metal layer is formed. An adhesion-enhancing layer is formed over the metal layer. A dielectric stack is formed over the adhesion-enhancing layer. A trench is formed in the dielectric stack. A barrier layer is formed conforming to the sidewall of the trench. A high-k dielectric layer is formed conforming to the barrier layer. A sacrificial layer is formed conforming to the high-k dielectric layer.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: September 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yao-Wen Chang, Gung-Pei Chang, Ching-Sheng Chu, Chern-Yow Hsu
  • Publication number: 20240263345
    Abstract: A silicon carbide crystal expansion apparatus includes a crucible and a heating device. The crucible includes a main body and a cover body. The main body has a raw material space suitable for placing a silicon carbide raw material. The cover body is suitable for being placed above the main body, and has an accommodating space suitable for a silicon carbide seed and a crystal expansion space located below the accommodating space. The heating device is thermally coupled to the crucible. The upper portion of the crystal expansion space has a first size, and the lower portion of the crystal expansion space has a second size, and the second size is larger than the first size.
    Type: Application
    Filed: May 22, 2023
    Publication date: August 8, 2024
    Applicant: Winsheng Material Technology (WMT) Co., Ltd.
    Inventors: Chi-Hang Hung, Min-Sheng Chu, Wei-Tse Hsu, Lei Fang
  • Publication number: 20240233437
    Abstract: Provided is a multi-scale model ensemble for detection of objects in images. The model ensemble can be applied, for example, in the context of performing object identification activities, such as positively identifying desired objects in image data or video data using a variety of different crop levels.
    Type: Application
    Filed: January 5, 2023
    Publication date: July 11, 2024
    Inventors: Yaojie Liu, Wen-Sheng Chu
  • Publication number: 20240193903
    Abstract: Provided are systems and methods for detecting an object in an image. The method can include receiving an input image and analyzing the input image using an image segmentation model to identify one or more indicative areas within the input image, the one or more indicative areas being indicative of one or more objects within the input image. The method can also include analyzing the one or more indicative areas of the input image using a convolutional model to generate at least one label for at least one portion of the one or more indicative areas of the input image, the label indicating whether a specific object is identified within the input image, and performing at least one action based on the at least one label for the at least one portion.
    Type: Application
    Filed: December 9, 2022
    Publication date: June 13, 2024
    Inventors: Skirmantas Kligys, Wen-Sheng Chu, Xiaoming Liu
  • Patent number: 12008821
    Abstract: Systems and methods of the present disclosure are directed to a computer-implemented method. The method can include obtaining a first image depicting a first object and a second image depicting a second object, wherein the first object comprises a first feature set and the second object comprises a second feature set. The method can include processing the first image with a machine-learned image transformation model comprising a plurality of model channels to obtain a first channel mapping indicative of a mapping between the plurality of model channels and the first feature set. The method can include processing the second image with the model to obtain a second channel mapping indicative of a mapping between the plurality of model channels and the second feature set. The method can include generating an interpolation vector for a selected feature.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: June 11, 2024
    Assignee: GOOGLE LLC
    Inventors: Wen-Sheng Chu, Abhishek Kumar, Min Jin Chong
  • Publication number: 20230415772
    Abstract: A trajectory planning system can be used to select a trajectory for an autonomous vehicle. The trajectory planning system may generate multiple trajectories and extract features from the generated trajectories. The trajectory planning system may evaluate the trajectories based on the extracted features and select a trajectory for the vehicle based on the evaluation. The selected trajectory may be used to control the vehicle.
    Type: Application
    Filed: June 24, 2022
    Publication date: December 28, 2023
    Inventors: Eric McKenzie Wolff, Tung Minh Phan, Ting-Sheng Chu, Momchil Tomov
  • Publication number: 20230369389
    Abstract: The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 16, 2023
    Inventors: Ching-Sheng Chu, Dun-Nian Yaung, Yu-Cheng Tsai, Meng-Hsien Lin, Ching-Chung Su, Jen-Cheng Liu, Wen-De Wang, Guan-Hua Chen
  • Publication number: 20230335543
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first dielectric structure having first inner sidewalls over an interlayer dielectric (ILD) structure. A second dielectric structure is over the first dielectric structure, where the first inner sidewalls are between second inner sidewalls of the second dielectric structure. A sidewall barrier structure is over the first dielectric structure and extends vertically along the second inner sidewalls. A lower bumping structure is between the second inner sidewalls and extends vertically along the first inner sidewalls and vertically along third inner sidewalls of the sidewall barrier structure. An upper bumping structure is over both the lower bumping structure and the sidewall barrier structure and between the second inner sidewalls, where an uppermost point of the upper bumping structure is at or below an uppermost point of the second dielectric structure.
    Type: Application
    Filed: June 9, 2023
    Publication date: October 19, 2023
    Inventors: Ching-Sheng Chu, Chern-Yow Hsu
  • Patent number: 11769791
    Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Sheng Chu, Dun-Nian Yaung, Yu-Cheng Tsai, Meng-Hsien Lin, Ching-Chung Su, Jen-Cheng Liu, Wen-De Wang, Guan-Hua Chen