Abstract: A circuit board device includes a multilayer board structure, a main ground and a circuit module. The main ground is configured in the multilayer board structure. The circuit module includes two differential-signal portions. These differential-signal portions are all located on one core layer of the multilayer board structure. Each of the differential-signal portions includes a differential through-hole pair and a plurality of ground through holes, and these ground through holes are arranged at intervals to surround the differential through-hole pair, and are electrically connected to the main ground. The patterns of the differential-signal portions are mirror symmetrical to each other based on an imaginary mirror line therebetween, and the minimum linear distances from the differential-signal portions to the imaginary mirror line are equal to each other.

Abstract: A semiconductor chiplet device includes a first die, a second die, a decoupling circuit and an interposer. The interposer includes a plurality of power traces and a plurality of ground traces. The first die and the second die are arranged on a first side of the interposer according to a configuration direction, and are coupled to the power traces and the ground traces. The decoupling circuit is arranged on a second side of the interposer, and is coupled to the power traces and the ground traces. The power traces and the ground traces are staggered with each other, and an extending direction of the ground traces and the power traces is the same as the configuration direction.

Abstract: A semiconductor chiplet device includes a package substrate, an interposer layer, a first die and a second die. The first die includes a first interface, and the second die includes a second interface. A first side of the interposer layer is configured to arrange the first die and the second die. The first die and the second die perform a data transmission through the first interface, the interposer layer and the second interface. The package substrate is arranged on a second side of the interposer layer, and includes a decoupling capacitor. The decoupling capacitor is arranged between the first interface and the second interface, or arranged in a vertical projection area of the first interface and the second interface on the package substrate.

Abstract: A high-frequency transmission element is provided. The high-frequency transmission element includes a connecting wire structure and an impedance matching plate structure. The connecting wire structure includes a connecting wire and a connecting pad. The connecting pad is located at an end of the connecting wire. The impedance matching plate structure includes an impedance matching plate body, an opening, and an impedance matching portion. The connecting pad is located in a projection range of the opening in a direction of orthographic projection of the impedance matching plate structure. The impedance matching portion is located in a periphery of the opening and extends in the direction from the connecting wire towards the connecting pad.

Abstract: A communication interface structure and a Die-to-Die package are provided. The communication interface structure includes first bumps arranged in a first row-column configuration, second bumps arranged in a second row-column configuration, and conductive lines disposed between the first bumps and the second bumps to connect each of the first bumps to each of the second bumps. The first bumps in neighboring rows are alternately shifted with each other. The second bumps are disposed under or over the first bumps, wherein each of the second bumps in even rows is at a position shifted in a column direction from a center of each of the first bumps in the even rows, and each of the second bumps in odd rows is at a position between two of the second bumps in the even rows in the column direction.

Abstract: A semiconductor packaging device includes a packaging module, a heat dissipation cover and a thermal interface material layer. The package module includes a substrate, and a working chip mounted on the substrate. The heat dissipation cover includes a metal cover fixed on the substrate and covering the working chip, an accommodating recess located on the metal cover to accommodate the working chip, and a plurality of protrusive columns respectively formed on the metal cover and distributed within the accommodating recess at intervals. The depth of the accommodating recess is greater than the height of each protrusive column, and the accommodating recess is greater than the working chip. The thermal interface material layer is non-solid, and located within the accommodating recess between the protrusive columns to wrap the protrusive columns and contact with the working chip, the metal cover and the protrusive columns.

Abstract: An interposer device comprises two bump regions, a channel region, a plurality of signal lines and a plurality of ground lines. The two bump regions are respectively coupled to two semiconductor devices. The channel region is connected between the two bump regions. The plurality of signal lines are embedded in the two bump regions and the channel region, and electrically connected to the two semiconductor devices for transmitting circuit signals. The plurality of ground lines are embedded in the two bump regions and the channel region for shielding the plurality of signal lines. In each bump region, each signal line comprises a trunk portion, a turning portion, and a signal turning point connected between the trunk portion and the turning portion. The trunk portion extends parallel to a first direction, and the turning portion extends parallel to a second direction.

Abstract: A communication interface structure and a Die-to-Die package are provided. The communication interface structure includes first bumps arranged in a first row-column configuration, second bumps arranged in a second row-column configuration, and conductive lines disposed between the first bumps and the second bumps to connect each of the first bumps to each of the second bumps. The first bumps in neighboring rows are alternately shifted with each other. The second bumps are disposed under or over the first bumps, wherein each of the second bumps in even rows is at a position shifted in a column direction from a center of each of the first bumps in the even rows, and each of the second bumps in odd rows is at a position between two of the second bumps in the even rows in the column direction.

Abstract: A semiconductor wiring substrate includes a first circuit layer, a second circuit layer and a first dielectric layer. The first circuit layer includes a plurality of first signal traces and a plurality of first ground traces, wherein the first signal traces and the first ground traces are alternatively arranged on the first circuit layer, and one of the first signal traces is spaced at a first spacing from adjacent one of the first ground traces. The first dielectric layer is between the first circuit layer and the second circuit layer and has a first thickness in an arrangement direction of the first circuit layer, the first dielectric layer and the second circuit layer, wherein the first spacing substantially ranges from 0.78 to 1.96 times the first thickness.

Abstract: An interposer routing structure includes a first trace layer, a bump layer, a second trace layer and a third trace layer. The first trace layer is configured to receive a power. The bump layer is coupled to a die. The second trace layer and the third trace layer are coupled between the first trace layer and the bump layer, and include multiple ground traces and multiple power traces. The ground traces are located on both sides of at least one of the power traces, so that the ground traces isolate the at least one power trace and multiple signal traces. The power traces of the second trace layer are coupled to each other by a connecting power trace, and the ground traces of the third trace layer are coupled to each other by a connecting ground trace.

Abstract: A semiconductor wiring substrate includes a first circuit layer, a second circuit layer and a first dielectric layer. The first circuit layer includes a plurality of first signal traces and a plurality of first ground traces, wherein the first signal traces and the first ground traces are alternatively arranged on the first circuit layer, and one of the first signal traces is spaced at a first spacing from adjacent one of the first ground traces. The first dielectric layer is between the first circuit layer and the second circuit layer and has a first thickness in an arrangement direction of the first circuit layer, the first dielectric layer and the second circuit layer, wherein the first spacing substantially ranges from 0.78 to 1.96 times the first thickness.

Abstract: A power distribution device includes a substrate, a first chip, a first bump, a second bump and a first capacitor. The first chip is configured to receive a first reference voltage signal and a second reference voltage signal. The first bump is located between the substrate and the first chip, and configured to transmit the first reference voltage signal from the substrate to the first chip. The second bump is located between the substrate and the first chip, and configured to transmit the second reference voltage signal from the substrate to the first chip. The first capacitor is located above the substrate and below the first chip. A first terminal of the first capacitor is coupled to the first bump, and a second terminal of the first capacitor is coupled to the second bump. A power distribution system is also disclosed herein.

Abstract: A semiconductor chiplet device includes a package substrate, an interposer layer, a first die and a second die. The first die includes a first interface, and the second die includes a second interface. A first side of the interposer layer is configured to arrange the first die and the second die. The first die and the second die perform a data transmission through the first interface, the interposer layer and the second interface. The package substrate is arranged on a second side of the interposer layer, and includes a decoupling capacitor. The decoupling capacitor is arranged between the first interface and the second interface, or arranged in a vertical projection area of the first interface and the second interface on the package substrate.

Abstract: A radio frequency energy-harvesting apparatus is applied to a radio frequency energy-transmitting apparatus with a location detection function. The radio frequency energy-harvesting apparatus includes a direct current signal receiving-processing unit, a rectification and harmonic generation unit, and a radar wave receiving-transmitting unit. The rectification and harmonic generation unit is electrically connected to the direct current signal receiving-processing unit. The radar wave receiving-transmitting unit is electrically connected to the rectification and harmonic generation unit.

Abstract: A power delivery device includes a printed circuit board (PCB), a package device, and a chip connecting device. The PCB is configured to receive a first reference voltage and a second reference voltage. The package device is coupled to the PCB, and includes a bump array. The chip connecting device is coupled to the bump array of the package device, and configured to output a first supply voltage and a second supply voltage. The bump array includes first bumps and second bumps. The first bumps are configured to transmit the first reference voltage. The second bumps are configured to transmit the second reference voltage. The first bumps and the second bumps are disposed in parallel.

Abstract: A signal transmission device includes a transmission line. The transmission line is configured to receive a signal transmitted from a transmission device, and output the signal to a receiving device. The transmission line includes a signal suppression device. The signal suppression device is coupled to the receiving device, and is configured to suppress a reflection signal reflected from the receiving device. The signal suppression device includes a pull-up element and a compensation element. The pull-up element is configured to decrease an equivalent impedance from the signal suppression device to the receiving device. The compensation element is configured to compensate for the equivalent impedance from the signal suppression device to the receiving device. A first terminal of the pull-up element is coupled to a first terminal of the compensation element, and a second terminal of the compensation element is coupled to the receiving device.

Abstract: An RF energy transmitting apparatus with positioning and polarization tracing function is used for an RF energy harvesting apparatus. The RF energy transmitting apparatus includes a power radar transmitter and a radar controller. The power radar transmitter receives a power source signal and emits an electromagnetic source wave. The radar controller is electrically connected to power radar transmitter and receives a reflected harmonic wave. The power radar transmitter emits the electromagnetic source wave to scan a space. The RF energy harvesting apparatus generates and emits the reflected harmonic wave. The radar controller determines a position and a polarization angle of the RF energy harvesting apparatus after receiving the reflected harmonic wave and to adjust a polarization angle of the power radar transmitter to be within a predetermined angle range with respect to the polarization angle of the reflected harmonic wave sent from the RF energy harvesting apparatus.

Abstract: A power delivery device includes a printed circuit board (PCB), a package device, and a chip connecting device. The PCB is configured to receive a first reference voltage and a second reference voltage. The package device is coupled to the PCB, and includes a bump array. The chip connecting device is coupled to the bump array of the package device, and configured to output a first supply voltage and a second supply voltage. The bump array includes first bumps and second bumps. The first bumps are configured to transmit the first reference voltage. The second bumps are configured to transmit the second reference voltage. The first bumps and the second bumps are disposed in parallel.

Abstract: A signal transmission device includes a transmission line. The transmission line is configured to receive a signal transmitted from a transmission device, and output the signal to a receiving device. The transmission line includes a signal suppression device. The signal suppression device is coupled to the receiving device, and is configured to suppress a reflection signal reflected from the receiving device. The signal suppression device includes a pull-up element and a compensation element. The pull-up element is configured to decrease an equivalent impedance from the signal suppression device to the receiving device. The compensation element is configured to compensate for the equivalent impedance from the signal suppression device to the receiving device. A first terminal of the pull-up element is coupled to a first terminal of the compensation element, and a second terminal of the compensation element is coupled to the receiving device.

Abstract: A circuit structure including a first signal line and a second signal line is provided. The first signal line includes a first line segment, a first ball grid array pad, and a first through hole disposed between the first line segment and the first ball grid array pad. The second signal line includes a second line segment, a second ball grid array pad, and a second through hole disposed between the second line segment and the second ball grid array pad. In a plan view, a line connecting the center of the first ball grid array pad and the center of the second ball grid array pad has a first distance, a line connecting the center of the first through hole and the center of the second through hole has a second distance, and the first distance is less than the second distance. A chip package is also provided.