Patents by Inventor Sheng-Fan Yang

Sheng-Fan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200059116
    Abstract: A radio frequency energy-harvesting apparatus is applied to a radio frequency energy-transmitting apparatus with a location detection function. The radio frequency energy-harvesting apparatus includes a direct current signal receiving-processing unit, a rectification and harmonic generation unit, and a radar wave receiving-transmitting unit. The rectification and harmonic generation unit is electrically connected to the direct current signal receiving-processing unit. The radar wave receiving-transmitting unit is electrically connected to the rectification and harmonic generation unit.
    Type: Application
    Filed: October 25, 2019
    Publication date: February 20, 2020
    Inventors: Tzuen-Hsi HUANG, Sheng-Fan YANG, Chun-Cheng CHEN, Pei-Jung CHUNG, Chun-Yi LU
  • Publication number: 20180205144
    Abstract: An RF energy transmitting apparatus is applied to an RF energy harvesting apparatus, the RF energy transmitting apparatus includes: a power radar transmitter receiving a power source signal and emits an electromagnetic source wave. A radar controller is electrically connected to the power radar transmitter and receives a reflected harmonic wave. After receiving the electromagnetic source wave, the RF energy harvesting apparatus generates and emits the reflected harmonic wave. After the radar controller receives the reflected harmonic wave, the radar controller determines a polarization angle of a reflection signal from the RF energy harvesting apparatus, and the radar controller adjusts the polarization angle of the antenna of the power radar transmitter to be within a predetermined range around the polarization angle of the reflected harmonic signal from the RF energy harvesting apparatus for an optimal received power.
    Type: Application
    Filed: November 29, 2017
    Publication date: July 19, 2018
    Inventors: Tzuen-Hsi HUANG, Sheng-Fan YANG, Chun-Cheng CHEN, Pei-Jung CHUNG, Fang-Ming WU
  • Publication number: 20170108585
    Abstract: A radio frequency energy-transmitting apparatus includes a harmonic radar unit and a harmonic radar control unit. The harmonic radar unit transmits a radar wave with a fundamental frequency. After a radio frequency energy-harvesting apparatus receives the radar wave, the radio frequency energy-harvesting apparatus generates and transmits a radar reflection harmonic wave. A frequency of the radar reflection harmonic wave is a multiple frequency of the radar wave. After the harmonic radar unit receives the radar reflection harmonic wave, the harmonic radar control unit determines a location of the radio frequency energy-harvesting apparatus. According to the location of the radio frequency energy-harvesting apparatus, the harmonic radar control unit controls the harmonic radar unit, so that a radar wave beam of the radar wave transmitted from the harmonic radar unit is directed toward the location of the radio frequency energy-harvesting apparatus.
    Type: Application
    Filed: December 1, 2015
    Publication date: April 20, 2017
    Inventors: Tzuen-Hsi HUANG, Sheng-Fan YANG, Chun-Cheng CHEN, Pei-Jung CHUNG, Chun-Yi LU
  • Publication number: 20140306920
    Abstract: A touch screen structure for receiving and processing touch signal is disclosed, in which the touch screen structure includes a substrate, a plurality of conductive patterns, a plurality of first routing traces, and a plurality of second routing traces. The conductive patterns are disposed on the substrate, in which each of the conductive patterns has a first side and a second side disposed opposite to the first side. The first routing traces are disposed on the substrate, in which the first routing traces are electrically connected to the first sides of the conductive patterns. The second routing traces are disposed on the substrate, in which the second routing traces are electrically connected to the second sides of the conductive patterns.
    Type: Application
    Filed: April 10, 2013
    Publication date: October 16, 2014
    Applicant: Himax Technologies Limited
    Inventors: Jui-Ni LEE, Sheng-Fan YANG, Yaw-Guang CHANG, Shen-Feng TAI, Cheng-Feng HSIEH
  • Publication number: 20130265247
    Abstract: A touch panel including a substrate and a sensing array is provided. The sensing array is disposed on the substrate and includes a plurality of sensing units. Each sensing unit has a first sensing electrode and a second sensing electrode which are arranged in a staggered manner and are electrically insulated from each other. The first sensing electrode includes two parallel first sensing pads and a first connection portion. The second sensing electrode includes two parallel second sensing pads and a second connection portion. The first sensing pads, the first connection portion, the second sensing pads, and the second connection portion are in rectangular shapes, and short sides of the first connection portion and the second connection portion are electrically connected to middle portions of long sides of the first sensing pads and the second sensing pads respectively. The second connection portion and the first connection portion intersect each other.
    Type: Application
    Filed: January 18, 2013
    Publication date: October 10, 2013
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: Sheng-Fan Yang, Jui-Ni Lee, Yaw-Guang Chang, Shen-Feng Tai
  • Publication number: 20130234979
    Abstract: A touch cell applied to a capacitive touch panel includes a first electrode and a second electrode, where the first electrode is connected to a scan signal transmitting circuit of the capacitive touch panel, and is utilized for receiving a scan signal, and the second electrode is connected to a detecting circuit of the capacitive touch panel. In addition, the second electrode is not connected to the first electrode, the second electrode has a fish-bone pattern, and a width of a tail of branches of the fish-bone pattern is greater than a width of a head of the branches of the fish-bone pattern.
    Type: Application
    Filed: November 22, 2012
    Publication date: September 12, 2013
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: Jui-Ni Lee, Sheng-Fan Yang, Yaw-Guang Chang, Shen-Feng Tai, Cheng-Feng Hsieh
  • Publication number: 20130050884
    Abstract: An ESD protection circuit connected between an I/O pad and an internal circuit is disclosed. The ESD protection circuit includes a P type ESD protection element which has a first P type doped region, a first isolation structure and a first N type doped region. The first isolation structure is disposed inside the first P type doped region, and the first N type doped region is disposed to encompass said first P type doped region. During an ESD event, the first P type doped region of the P type ESD protection element receives an ESD current and drains it away, and the parasitical capacitance of the P type ESD protection element decreases based on the area of the first P type doped region.
    Type: Application
    Filed: August 23, 2011
    Publication date: February 28, 2013
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: Ching-Ling Tsai, Sheng-Fan Yang, Shih-Fan Chen
  • Patent number: 8332804
    Abstract: The invention discloses a chipset having N input/output (I/O) ports coupled to a voltage source which have an observation I/O port. The method includes calculating a first set of impedances at a predetermined frequency or the observation I/O port, if the voltage source is internally coupled to the N I/O ports within the chipset, and calculating a second set of impedances at the predetermined frequency for the observation I/O port, if the voltage source is externally coupled to the N I/O ports through a carrier coupling the core chip to the voltage source. The first set of impedances are compared to the second set of impedances, and the impedance of the power network or the impedance of the carrier is adjusted according to the comparison result.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: December 11, 2012
    Assignee: Himax Technologies Limited
    Inventors: Hsing-Chou Hsu, Tung-Yang Chen, Sheng-Fan Yang
  • Publication number: 20120176150
    Abstract: A measuring equipment, such as a vector network analyzer, is provided. The measuring equipment includes a first port and a second port, a probe connected to the first port, an antenna connected to the second port, and a test board corresponding to a type of a device-under-test. A probe-effect is obtained by measuring the test board via the probe and the antenna.
    Type: Application
    Filed: January 10, 2011
    Publication date: July 12, 2012
    Inventors: Hsing-Chou Hsu, Sheng-Fan Yang, Wei-Da Guo, Jui-Ni Lee, Tung-Yang Chen
  • Publication number: 20120159413
    Abstract: The invention discloses a chipset having N input/output (I/O) ports coupled to a voltage source which have an observation I/O port. The method includes calculating a first set of impedances at a predetermined frequency or the observation I/O port, if the voltage source is internally coupled to the N I/O ports within the chipset, and calculating a second set of impedances at the predetermined frequency for the observation I/O port, if the voltage source is externally coupled to the N I/O ports through a carrier coupling the core chip to the voltage source. The first set of impedances are compared to the second set of impedances, and the impedance of the power network or the impedance of the carrier is adjusted according to the comparison result.
    Type: Application
    Filed: February 29, 2012
    Publication date: June 21, 2012
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: Hsing-Chou HSU, Tung-Yang CHEN, Sheng-Fan YANG
  • Patent number: 8196078
    Abstract: A method for predicting and debugging electromagnetic interference (EMI) characteristics of an integrated circuit (IC) system includes the following steps: selecting a frequency domain range according to transformed raw data of the IC system to generate a blocking frequency analysis result, wherein the transformed raw data are transformed by a time-frequency waveform transformation; setting criteria data; comparing the blocking frequency analysis result with the criteria data to generate at least one comparison result; and generating a pass analysis report when a processing unit determines that each comparison result is passed; otherwise, executing an EMI design time-frequency analysis.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: June 5, 2012
    Assignee: Himax Technologies Limited
    Inventors: Tung-Yang Chen, Ching-Ling Tsai, Sheng-Fan Yang, Jui-Ni Lee
  • Patent number: 8151241
    Abstract: The invention discloses an impedance design method for a power network of a core chip within a chipset having N input/output (I/O) ports coupled to a voltage source which have an observation I/O port. The method includes calculating a first set of impedances at a predetermined frequency or the observation I/O port, if the voltage source is internally coupled to the N I/O ports within the chipset, and calculating a second set of impedances at the predetermined frequency for the observation I/O port, if the voltage source is externally coupled to the N I/O ports through a carrier coupling the core chip to the voltage source. The first set of impedances to the second set of impedances are compared, and the impedance of the power network or the impedance of the carrier is adjusted according to the comparison result.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: April 3, 2012
    Assignee: Himax Technologies Limited
    Inventors: Hsing-Chou Hsu, Tung-Yang Chen, Sheng-Fan Yang
  • Publication number: 20110185336
    Abstract: The invention discloses an impedance design method for a power network of a core chip within a chipset having N input/output (I/O) ports coupled to a voltage source which have an observation I/O port. The method includes calculating a first set of impedances at a predetermined frequency or the observation I/O port, if the voltage source is internally coupled to the N I/O ports within the chipset, and calculating a second set of impedances at the predetermined frequency for the observation I/O port, if the voltage source is externally coupled to the N I/O ports through a carrier coupling the core chip to the voltage source. The first set of impedances to the second set of impedances are compared, and the impedance of the power network or the impedance of the carrier is adjusted according to the comparison result.
    Type: Application
    Filed: January 26, 2010
    Publication date: July 28, 2011
    Applicant: HIMAX TECHNOLOGIES LIMTED
    Inventors: Hsing-Chou Hsu, Tung-Yang Chen, Sheng-Fan Yang
  • Publication number: 20100235798
    Abstract: A method for predicting and debugging electromagnetic interference (EMI) characteristics of an integrated circuit (IC) system includes the following steps: selecting a frequency domain range according to transformed raw data of the IC system to generate a blocking frequency analysis result, wherein the transformed raw data are transformed by a time-frequency waveform transformation; setting criteria data; comparing the blocking frequency analysis result with the criteria data to generate at least one comparison result; and generating a pass analysis report when a processing unit determines that each comparison result is passed; otherwise, executing an EMI design time-frequency analysis.
    Type: Application
    Filed: February 11, 2010
    Publication date: September 16, 2010
    Inventors: Tung-Yang Chen, Ching-Ling Tsai, Sheng-Fan Yang, Jui-Ni Lee