Abstract: A display device is disclosed, which comprises: a first substrate; a second substrate disposed adjacent to the first substrate and partially covering the first substrate, wherein the second substrate comprises a second arc edge and a second side, and the second arc edge connects to the second side; a driving unit disposed on a part of the first substrate uncovered with the second substrate; and a compensation panel disposed on the driving unit and comprising a third arc edge and a third side, wherein the third arc edge connects to the third side, wherein the third side corresponds to the second side, and the third arc edge corresponds to the second arc edge.

Abstract: A display panel includes shift registers coupled in serial. At least one of the shift registers includes an input circuit, an output circuit and a control circuit. The input circuit is coupled to a first input terminal and a second input terminal for respectively receiving a first input signal and a second input signal. The output circuit is coupled to a first clock input terminal for receiving a first clock signal and outputting a pulse signal at an output terminal according to the first clock signal. The control circuit is coupled to the output circuit via a first control node, a second control node and a third control node and controls voltages at the first control node, the second control node and the third control node according to the first input signal or the second input signal, and further controls operations of the output circuit.

Abstract: A transflective type liquid crystal panel includes a plurality of sub-pixels arranged in rows and columns to form a sub-pixel array, a plurality of first wires extending along the row direction or the column direction, and a plurality of second wires which are parallel with the first wires. The plurality of sub-pixels includes transmissive sub-pixels and reflective sub-pixels. Each row and column in the sub-pixel array has both transmissive sub-pixels and reflective sub-pixels. The transmissive sub-pixels are connected to and driven by the first wires, and the reflective sub-pixels are connected to and driven by the second wires.

Abstract: A touch sensing display and a sensing method thereof are provided. The touch sensing display includes a touch sensor layer and an active shield layer. The active shield layer includes a plurality of gate lines and a common electrode. The sensing method comprises the following steps. A touch sensing signal is applied to the touch sensor layer during a touch mode period. A gate signal of the gate lines is controlled to be synchronous to the touch sensing signal during the touch mode period. A common signal of the common electrode is controlled to be synchronous to the touch sensing signal during the touch mode period.

Abstract: A display panel structure includes a substrate, plural gate lines and data lines arranged on the substrate, plural pixel units, and plural dummy pixel units. The substrate has a display region and a peripheral region surrounding the display region. The gate lines and data lines are extended from the display region to the peripheral region. The pixel units are disposed at the display region. The dummy pixel units are disposed at the peripheral region, and include a first region, a second region, and a third region. The dummy pixel units of the first region and the second region are arranged along a first direction and a second direction, respectively. The dummy pixel units of the third region are arranged between the first and second regions. The dummy pixel units of the third region include one of the gate lines and one of the data lines.

Abstract: A display panel device with multiple electrostatic discharge rings includes a substrate, a display circuit, a first electrostatic discharge ring, and a second electrostatic discharge ring. The display circuit is arranged on the substrate and includes a semiconductor layer and a metal layer. The first electrostatic discharge ring is arranged at the same layer with the metal layer on the substrate for surrounding the display circuit. The second electrostatic discharge ring is arranged at the same layer with the semiconductor layer on the substrate for surrounding the first electrostatic discharge ring.

Abstract: A shift register apparatus including a first shift register cell is disclosed. The first shift register cell includes a first logic unit, a first control unit and a first output unit. The first logic unit generates a first control signal and a second control signal according to a start signal and a first setting signal. During a first period, the first control unit employs the first and second control signals to make a first clock signal update the first setting signal and the first output unit employs the first and second control signals to make a second clock signal update the first shifted signal. During a second period, the first output unit controls the first shifted signal according to the first and second control signals such that the first shifted signal does not follow the second clock signal.

Abstract: An image display system includes a gate driving circuit and a data driving circuit. The gate driving circuit generates gate driving signals to drive pixels in a pixel array. The data driving circuit generates data driving signals to provide data to the pixels. At least one of the gate and data driving circuits includes a shift register. The shift register includes flip-flops coupled in serial. Each flip-flop generates output signals in response to an input signal, and is reset in response to a reset signal. One of the flip-flops receives a first output signal of a last stage flip-flop as the reset signal thereof, and at least one flip-flop following the flip-flop receiving the first output signal of the last stage flip-flop receives a second output signal of the flip-flop receiving the first output signal of the last stage flip-flop as the reset signal thereof.

Abstract: A bi-directional shift register circuit includes multiple stages of shift registers for generating multiple gate driving signals. At least one shift register includes an input stage circuit, an output stage circuit, a first and a second transistor. The input stage circuit is coupled to a first and a second signal input terminal. The output stage circuit receives a first clock signal and generating a corresponding gate driving signal. The first transistor includes a first terminal coupled to a first node, a second terminal coupled to a second node and a third terminal coupled to a high operation voltage. The second transistor includes a first terminal coupled to the second node, a second terminal coupled to the first node and a third terminal coupled to the high operation voltage. The first transistor charges the first node and the second transistor discharges the second node.

Abstract: A gate driving device includes a gate driving unit, a first control unit, a second control unit and a switch unit. The first control unit includes an input terminal receiving a first output signal and a first clock input terminal receiving a first clock signal. The second control unit includes an input terminal receiving a second output signal and a first clock input terminal receiving a second clock signal. The switch unit, the first control unit and the second control unit are coupled to a carryout signal output node for generating a carryout signal at the carryout signal output node which indicates whether the gate driving unit is functioning correctly. The first output signal and the second output signal of the gate driving unit are respectively one signal generated by any two different stages of shift register in the gate driving unit.

Abstract: A buffer generating an output signal and including a pull-high module and a pull-low module is disclosed. The pull-high module makes the output signal to have a rising edge. The pull-low module makes the output signal to have a falling edge. The falling edge includes a plurality of falling portions. A slope of a first falling portion of the falling portions is different from a slope of a second falling portion of the falling portions.

Abstract: A gate driving device includes a gate driving unit, a first control unit, a second control unit and a switch unit. The first control unit includes an input terminal receiving a first output signal and a first clock input terminal receiving a first clock signal. The second control unit includes an input terminal receiving a second output signal and a first clock input terminal receiving a second clock signal. The switch unit, the first control unit and the second control unit are coupled to a carryout signal output node for generating a carryout signal at the carryout signal output node which indicates whether the gate driving unit is functioning correctly. The first output signal and the second output signal of the gate driving unit are respectively one signal generated by any two different stages of shift register in the gate driving unit.

Abstract: A bi-directional shift register circuit includes multiple stages of shift registers for generating multiple gate driving signals. At least one shift register includes an input stage circuit, an output stage circuit, a first and a second transistor. The input stage circuit is coupled to a first and a second signal input terminal The output stage circuit receives a first clock signal and generating a corresponding gate driving signal. The first transistor includes a first terminal coupled to a first node, a second terminal coupled to a second node and a third terminal coupled to a high operation voltage. The second transistor includes a first terminal coupled to the second node, a second terminal coupled to the first node and a third terminal coupled to the high operation voltage. The first transistor charges the first node and the second transistor discharges the second node.

Abstract: A bi-directional shift register circuit includes multiple stages of shift registers coupled in serial for generating multiple gate driving signals according to two clock signals. At least one of the shift registers includes a transmission gate and a latch. The transmission gate is turned on or off according to a start pulse of a start signal or a gate pulse of the gate driving signal output by at least one adjacent shift register, so as to output one of a first clock signal and a second clock signal as the corresponding gate driving signal. The latch is coupled to an output node for outputting the corresponding gate driving signal. The output node is further coupled to the transmission gate of at least one adjacent shift register.

Abstract: A shift register apparatus including a first shift register cell is disclosed. The first shift register cell includes a first logic unit, a first control unit and a first output unit. The first logic unit generates a first control signal and a second control signal according to a start signal and a first setting signal. During a first period, the first control unit employs the first and second control signals to make a first clock signal update the first setting signal and the first output unit employs the first and second control signals to make a second clock signal update the first shifted signal. During a second period, the first output unit controls the first shifted signal according to the first and second control signals such that the first shifted signal does not follow the second clock signal.

Abstract: An image display system includes a gate driving circuit and a data driving circuit. The gate driving circuit generates gate driving signals to drive pixels in a pixel array. The data driving circuit generates data driving signals to provide data to the pixels. At least one of the gate and data driving circuits includes a shift register. The shift register includes flip-flops coupled in serial. Each flip-flop generates output signals in response to an input signal, and is reset in response to a reset signal. One of the flip-flops receives a first output signal of a last stage flip-flop as the reset signal thereof, and at least one flip-flop following the flip-flop receiving the first output signal of the last stage flip-flop receives a second output signal of the flip-flop receiving the first output signal of the last stage flip-flop as the reset signal thereof.

Abstract: A buffer generating an output signal and including a pull-high module and a pull-low module is disclosed. The pull-high module makes the output signal to have a rising edge. The pull-low module makes the output signal to have a falling edge. The falling edge includes a plurality of falling portions. A slope of a first falling portion of the falling portions is different from a slope of a second falling portion of the falling portions.

Abstract: The present invention provides an image display system that includes a charge pump circuit. The charge pump circuit further includes a first inverter, a first switch, and a capacitor. The first inverter has a first input terminal and a first output terminal. The first input terminal receives a first clock signal with a first voltage swing and the first output terminal outputs the first inverse clock signal by inversely converting the phase of the first clock signal. The first switch has a first switch input terminal, a first control terminal and a first switch output terminal. The first input terminal receives an input voltage. The first control terminal is coupled to the first output terminal and controls the first switch according to the first inverse clock voltage signal. A terminal of the capacitor receives a second clock signal with a second voltage swing and the other terminal of the first capacitor is coupled to the first switch output terminal to provide the first output voltage.

Abstract: The present invention relates to a discharge circuit of a liquid crystal display device which receives a power and controls the charges stored in the pixel units of the pixel matrix of the liquid crystal display device. The discharge circuit includes a control circuit receiving the power and generating a control signal when being disconnected from the power, a horizontal driver and a pre-charge circuit forming a plurality of discharge paths having switches, and a selection circuit receiving the control signal and generating a selection signal for enabling the switches of the discharge paths.

Abstract: A control method applied to a display panel including a gate driver, a source driver, and a plurality of pixel units. Each pixel unit includes a storage capacitor. At a first time point, a scan signal is provided by the gate driver. At a second time point following the first time point, at least one data signal is provided by the source driver. The storage capacitor stores a corresponding voltage according to the data signal and a common voltage. At the second time point, the common voltage is stable.