Patents by Inventor Sheng-Hsuan Lin

Sheng-Hsuan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10763116
    Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hong-Ying Lin, Cheng-Yi Wu, Alan Tu, Chung-Liang Cheng, Li-Hsuan Chu, Ethan Hsiao, Hui-Lin Sung, Sz-Yuan Hung, Sheng-Yung Lo, C. W. Chiu, Chih-Wei Hsieh, Chin-Szu Lee
  • Publication number: 20200270751
    Abstract: An enclosed-channel reactor system is provided, which includes: a reactor body having a plurality of enclosed channels therein; an upper cap disposed at one end of the reactor body and having an inlet port communicating with the plurality of enclosed channels; a lower cap disposed at the other end of the reactor body opposite to the upper cap and having an outlet port communicating with the plurality of enclosed channels; and at least a conduit plate disposed between the upper cap and the reactor body for guiding a precursor injected from the inlet port into the plurality of enclosed channels uniformly.
    Type: Application
    Filed: May 1, 2020
    Publication date: August 27, 2020
    Inventors: Tsong-Pyng Perng, Chi-Chung Kei, Chien-Pao Lin, Mrinalini Mishra, Sheng-Hsin Huang, Kuang-I Liu, Yu-Hsuan Yu
  • Patent number: 10756017
    Abstract: Contact structures and methods of forming contacts structures are contemplated by this disclosure. A structure includes a dielectric layer over a substrate, an adhesion layer, a silicide, a barrier layer, and a conductive material. The dielectric layer has an opening to a surface of the substrate. The adhesion layer is along sidewalls of the opening. The silicide is on the surface of the substrate. The barrier layer is on the adhesion layer and the silicide, and the barrier layer directly adjoins the silicide. The conductive material is on the barrier layer in the opening.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Mei-Hui Fu, Sheng-Hsuan Lin
  • Patent number: 10719138
    Abstract: An interactive electronic apparatus and an interactive method thereof are provided. The interactive electronic apparatus includes a main device and a casing. The main device is installed in a containing space of the casing. After the main device establishes a connection with the casing, the casing sends at least one of a first distance between the casing and an object to be sensed by a first distance sensor and a second distance between a bottom portion of the casing and a plane detected by a second distance sensor to the main device. The main device determines an interactive state of interaction with the interactive electronic apparatus based on at least one of a movement information sensed by a gravity sensor, the first distance and the second distance, and sends an interactive signal corresponding to the interactive state.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: July 21, 2020
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Cheng-Yuan Wei, Kai-Yi Chen, Wen-Yi Chiu, Hsiu-Hang Lin, Sheng-Chieh Tang, Kun-Hsuan Chang
  • Patent number: 10676824
    Abstract: An enclosed-channel reactor system is provided, which includes: a reactor body having a plurality of enclosed channels therein; an upper cap disposed at one end of the reactor body and having an inlet port communicating with the plurality of enclosed channels; a lower cap disposed at the other end of the reactor body opposite to the upper cap and having an outlet port communicating with the plurality of enclosed channels; and at least a conduit plate disposed between the upper cap and the reactor body for guiding a precursor injected from the inlet port into the plurality of enclosed channels uniformly.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: June 9, 2020
    Assignee: National Tsing Hua University
    Inventors: Tsong-Pyng Perng, Chi-Chung Kei, Chien-Pao Lin, Mrinalini Mishra, Sheng-Hsin Huang, Kuang-I Liu, Yu-Hsuan Yu
  • Patent number: 10659780
    Abstract: A de-blocking method is applied to a reconstructed projection-based frame having a first projection face and a second projection face, and includes obtaining a first spherical neighboring block for a first block with a block edge to be de-blocking filtered, and selectively applying de-blocking to the block edge of the first block for at least updating a portion of pixels of the first block. There is image content discontinuity between a face boundary of the first projection face and a face boundary of the second projection face. The first block is a part of the first projection face, and the block edge of the first block is a part of the face boundary of the first projection face. A region on a sphere to which the first spherical neighboring block corresponds is adjacent to a region on the sphere from which the first projection face is obtained.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: May 19, 2020
    Assignee: MEDIATEK INC.
    Inventors: Sheng-Yen Lin, Jian-Liang Lin, Cheng-Hsuan Shih
  • Publication number: 20200152763
    Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Inventors: Yu-Wen Cheng, Cheng-Tung Lin, Chih-Wei Chang, Hong-Mao Lee, Ming-Hsing Tsai, Sheng-Hsuan Lin, Wei-Jung Lin, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Wei-Yip Loh, Ya-Yi Cheng
  • Publication number: 20200150523
    Abstract: An extreme ultraviolet (EUV) mask is received. The EUV mask has an EUV pellicle disposed thereover. The EUV pellicle is coupled to the EUV mask at least in part via glue that is disposed on the EUV mask. The EUV pellicle is removed, thereby exposing the glue. A localized glue-removal process is performed by targeting a region of the EUV mask on which the glue is disposed. The localized glue-removal process is performed without affecting other regions of the EUV mask that do not have the glue disposed thereon. The localized glue-removal process may include injecting a cleaning chemical onto the glue and removing a waste chemical produced by the cleaning chemical and the glue. The localized glue-removal process may also include a plasma process that applies plasma to the glue. The localized glue-removal process may further include a laser process that shoots a focused laser beam at the glue.
    Type: Application
    Filed: December 27, 2019
    Publication date: May 14, 2020
    Inventors: Tzu-Ting Chou, Chung-Hsuan Liu, Kuan-Wen Lin, Chi-Lun Lu, Ting-Hao Hsu, Sheng-Chi Chin
  • Publication number: 20200111739
    Abstract: A method for forming a semiconductor contact structure is provided. The method includes depositing a dielectric layer over a substrate. The method also includes etching the dielectric layer to expose a sidewall of the dielectric layer and a top surface of the substrate. In addition, the method includes forming a silicide region in the substrate. The method also includes applying a plasma treatment to the sidewall of the dielectric layer and the top surface of the substrate to form a nitridation region adjacent to a periphery of the silicide region. The method further includes depositing an adhesion layer on the dielectric layer and the silicide region.
    Type: Application
    Filed: December 9, 2019
    Publication date: April 9, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Wen CHENG, Wei-Yip LOH, Yu-Hsiang LIAO, Sheng-Hsuan LIN, Hong-Mao LEE, Chun-I TSAI, Ken-Yu CHANG, Wei-Jung LIN, Chih-Wei CHANG, Ming-Hsing TSAI
  • Publication number: 20200103984
    Abstract: An interactive electronic apparatus and an interactive method thereof are provided. The interactive electronic apparatus includes a main device and a casing. The main device is installed in a containing space of the casing. After the main device establishes a connection with the casing, the casing sends at least one of a first distance between the casing and an object to be sensed by a first distance sensor and a second distance between a bottom portion of the casing and a plane detected by a second distance sensor to the main device. The main device determines an interactive state of interaction with the interactive electronic apparatus based on at least one of a movement information sensed by a gravity sensor, the first distance and the second distance, and sends an interactive signal corresponding to the interactive state.
    Type: Application
    Filed: April 23, 2019
    Publication date: April 2, 2020
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Cheng-Yuan Wei, Kai-Yi Chen, Wen-Yi Chiu, Hsiu-Hang Lin, Sheng-Chieh Tang, Kun-Hsuan Chang
  • Publication number: 20200043739
    Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.
    Type: Application
    Filed: October 8, 2019
    Publication date: February 6, 2020
    Inventors: Hong-Ying LIN, Cheng-Yi WU, Alan TU, Chung-Liang CHENG, Li-Hsuan CHU, Ethan HSIAO, Hui-Lin SUNG, Sz-Yuan HUNG, Sheng-Yung LO, C.W. CHIU, Chih-Wei Hsieh, Chin-Szu LEE
  • Patent number: 10535748
    Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Wen Cheng, Cheng-Tung Lin, Chih-Wei Chang, Hong-Mao Lee, Ming-Hsing Tsai, Sheng-Hsuan Lin, Wei-Jung Lin, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Wei-Yip Loh, Ya-Yi Cheng
  • Patent number: 10520805
    Abstract: An extreme ultraviolet (EUV) mask having a pellicle disposed thereover is received. The EUV pellicle is coupled to the EUV mask at least in part via glue that is disposed on the EUV mask. The EUV pellicle is removed, thereby exposing the glue. A localized glue-removal process is performed by targeting a region of the EUV mask on which the glue is disposed. The localized glue-removal process is performed without affecting other regions of the EUV mask that do not have the glue disposed thereon. The localized glue-removal process may include injecting a cleaning chemical onto the glue and removing a waste chemical produced by the cleaning chemical and the glue. The localized glue-removal process may also include a plasma process that applies plasma to the glue. The localized glue-removal process may further include a laser process that shoots a focused laser beam at the glue.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzu-Ting Chou, Chung-Hsuan Liu, Kuan-Wen Lin, Chi-Lun Lu, Ting-Hao Hsu, Sheng-Chi Chin
  • Patent number: 10504834
    Abstract: A semiconductor device and method of forming the same that includes forming a dielectric layer over a substrate and patterning a contact region in the dielectric layer, the contact region having side portions and a bottom portion that exposes the substrate. The method can also include forming a dielectric barrier layer in the contact region to cover the side portions and the bottom portion, and etching the dielectric barrier layer to expose the substrate. Subsequently, a conductive layer can be formed to cover the side portions and the bottom portion of the contact region and the conductive layer can be annealed to form a silicide region in the substrate beneath the bottom portion of the contact region, and the conductive layer can then be selectively removed on the side portions of the contact region.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Wen Cheng, Wei-Yip Loh, Yu-Hsiang Liao, Sheng-Hsuan Lin, Hong-Mao Lee, Chun-I Tsai, Ken-Yu Chang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Patent number: 10504778
    Abstract: An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Publication number: 20190328231
    Abstract: Repetitive electrical activity produces microstructural alteration in myelinated axons. These transient microstructural changes can be non-invasively visualized via two different magnetic-resonance-based approaches: diffusion fMRI and dynamic T2 spectroscopy in the ex vivo perfused bullfrog sciatic nerves. Non-invasive diffusion fMRI, based on standard diffusion tensor imaging (DTI), clearly localized the sites of axonal conduction blockage as might be encountered in neurotrauma or other lesion types. Diffusion fMRI response was graded in proportion to the total number of electrical impulses carried through a given locus. Diffusion basis spectrum imaging (DBSI) method revealed a reversible shift of tissue water into a restricted isotropic diffusion signal component, consistent with sub-myelinic vacuole formation.
    Type: Application
    Filed: April 29, 2019
    Publication date: October 31, 2019
    Applicant: Washington University
    Inventors: Sheng-Kwei Song, William M. Spees, Tsen-Hsuan Lin, Peng Sun, Chunyu Song
  • Publication number: 20190281293
    Abstract: A de-blocking method is applied to a reconstructed projection-based frame having a first projection face and a second projection face, and includes obtaining a first spherical neighboring block for a first block with a block edge to be de-blocking filtered, and selectively applying de-blocking to the block edge of the first block for at least updating a portion of pixels of the first block. There is image content discontinuity between a face boundary of the first projection face and a face boundary of the second projection face. The first block is a part of the first projection face, and the block edge of the first block is a part of the face boundary of the first projection face. A region on a sphere to which the first spherical neighboring block corresponds is adjacent to a region on the sphere from which the first projection face is obtained.
    Type: Application
    Filed: March 8, 2019
    Publication date: September 12, 2019
    Inventors: Sheng-Yen Lin, Jian-Liang Lin, Cheng-Hsuan Shih
  • Publication number: 20190273147
    Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 5, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Wen CHENG, Cheng-Tung LIN, Chih-Wei CHANG, Hong-Mao LEE, Ming-Hsing TSAI, Sheng-Hsuan LIN, Wei-Jung LIN, Yan-Ming TSAI, Yu-Shiuan WANG, Hung-Hsu CHEN, Wei-Yip LOH, Ya-Yi CHENG
  • Publication number: 20190273042
    Abstract: A semiconductor device and method of forming the same that includes forming a dielectric layer over a substrate and patterning a contact region in the dielectric layer, the contact region having side portions and a bottom portion that exposes the substrate. The method can also include forming a dielectric barrier layer in the contact region to cover the side portions and the bottom portion, and etching the dielectric barrier layer to expose the substrate. Subsequently, a conductive layer can be formed to cover the side portions and the bottom portion of the contact region and the conductive layer can be annealed to form a silicide region in the substrate beneath the bottom portion of the contact region, and the conductive layer can then be selectively removed on the side portions of the contact region.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 5, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Wen Cheng, Wei-Yip Loh, Yu-Hsiang Liao, Sheng-Hsuan Lin, Hong-Mao Lee, Chun-I Tsai, Ken-Yu Chang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Publication number: 20190252248
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Yu-Hung Lin, You-Hua Chou, Sheng-Hsuan Lin, Chih-Wei Chang