Patents by Inventor Sheng-Hsuan Lin

Sheng-Hsuan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250066899
    Abstract: A method includes: positioning a wafer on an electrostatic chuck of a physical vapor deposition apparatus, the wafer including an opening exposing a conductive feature; setting a temperature of the wafer to a room temperature; forming a tungsten thin film in the opening by the physical vapor deposition apparatus, the tungsten thin film including a bottom portion that is on an upper surface of the conductive feature exposed by the opening, a top portion that is on an upper surface of a dielectric layer through which the opening extends and a sidewall portion that is on a sidewall of the dielectric layer exposed by the opening; removing the top portion and the sidewall portion of the tungsten thin film from over the opening; and forming a tungsten plug in the opening on the bottom portion by selectively depositing tungsten by a chemical vapor deposition operation.
    Type: Application
    Filed: August 23, 2023
    Publication date: February 27, 2025
    Inventors: Chun-Yen LIAO, I. LEE, Shu-Lan CHANG, Sheng-Hsuan LIN, Feng-Yu CHANG, Wei-Jung LIN, Chun-I TSAI, Chih-Chien CHI, Ming-Hsing TSAI, Pei Shan CHANG, Chih-Wei CHANG
  • Publication number: 20250063783
    Abstract: A device includes a fin extending from a semiconductor substrate, a gate stack over and along a sidewall of the fin, an isolation region surrounding the gate stack, an epitaxial source/drain region in the fin and adjacent the gate stack, and a source/drain contact extending through the isolation region, including a first silicide region in the epitaxial source/drain region, the first silicide region including NiSi2, a second silicide region on the first silicide region, the second silicide region including TiSix, and a conductive material on the second silicide region.
    Type: Application
    Filed: November 5, 2024
    Publication date: February 20, 2025
    Inventors: Yan-Ming Tsai, Chih-Wei Chang, Ming-Hsing Tsai, Sheng-Hsuan Lin, Hung-Hsu Chen, Wei-Yip Loh
  • Patent number: 12218012
    Abstract: A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yip Loh, Yan-Ming Tsai, Hung-Hsu Chen, Chih-Wei Chang, Sheng-Hsuan Lin
  • Patent number: 12191199
    Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: January 7, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tien-Pei Chou, Ken-Yu Chang, Sheng-Hsuan Lin, Yueh-Ching Pai, Yu-Ting Lin
  • Patent number: 12166078
    Abstract: A device includes a fin extending from a semiconductor substrate, a gate stack over and along a sidewall of the fin, an isolation region surrounding the gate stack, an epitaxial source/drain region in the fin and adjacent the gate stack, and a source/drain contact extending through the isolation region, including a first silicide region in the epitaxial source/drain region, the first silicide region including NiSi2, a second silicide region on the first silicide region, the second silicide region including TiSix, and a conductive material on the second silicide region.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yan-Ming Tsai, Chih-Wei Chang, Ming-Hsing Tsai, Sheng-Hsuan Lin, Hung-Hsu Chen, Wei-Yip Loh
  • Publication number: 20240395611
    Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in a dielectric layer to expose a source/drain epitaxial layer in a substrate. An aspect ratio of the contact opening is between about 3 and about 10. The method further includes forming a first metal layer in the contact opening and in contact with the source/drain epitaxial layer, forming a barrier layer on the first metal layer, forming a liner layer on the barrier layer, forming second metal layer on the liner layer to partially fill the contact opening, and forming a third metal layer on the second metal layer to fill the contact opening.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tien-Pei CHOU, Ken-Yu CHANG, Sheng-Hsuan LIN, Yueh-Ching PAI, Yu-Ting LIN
  • Publication number: 20240355740
    Abstract: A method includes forming a dielectric layer over a conductive feature, and etching the dielectric layer to form an opening. The conductive feature is exposed through the opening. The method further includes forming a tungsten liner in the opening, wherein the tungsten liner contacts sidewalls of the dielectric layer, depositing a tungsten layer to fill the opening, and planarizing the tungsten layer. Portions of the tungsten layer and the tungsten liner in the opening form a contact plug.
    Type: Application
    Filed: June 30, 2023
    Publication date: October 24, 2024
    Inventors: Feng-Yu Chang, Sheng-Hsuan Lin, Shu-Lan Chang, Kai-Yi Chu, Meng-Hsien Lin, Pei-Hsuan Lee, Pei Shan Chang, Chih-Chien Chi, Chun-I Tsai, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai, Syun-Ming Jang, Wei-Jen Lo
  • Publication number: 20240136227
    Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Inventors: Ching-Yi Chen, Sheng-Hsuan Lin, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang
  • Publication number: 20240087953
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou
  • Patent number: 11901229
    Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Yi Chen, Sheng-Hsuan Lin, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang
  • Patent number: 11854874
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou
  • Publication number: 20230378325
    Abstract: Semiconductor device structure and methods of forming the same are described. The structure includes a dielectric layer disposed over an epitaxy source/drain region and a conductive feature disposed in the dielectric layer. The conductive feature includes a metal liner including a first material and a metal fill surrounded by the metal liner. The metal fill includes the first material having a first grain size. The conductive feature further includes a metal cap disposed on the metal liner and the metal fill, and the metal cap includes the first material having a second grain size different from the first grain size.
    Type: Application
    Filed: May 23, 2022
    Publication date: November 23, 2023
    Inventors: Sheng-Hsuan LIN, Feng-Yu CHANG, Shu-Lan CHANG, I Lee, Chun-Yen LIAO
  • Publication number: 20230369130
    Abstract: A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Wei-Yip Loh, Yan-Ming Tsai, Hung-Hsu Chen, Chih-Wei Chang, Sheng-Hsuan Lin
  • Patent number: 11810826
    Abstract: A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yip Loh, Yan-Ming Tsai, Hung-Hsu Chen, Chih-Wei Chang, Sheng-Hsuan Lin
  • Publication number: 20220367667
    Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 17, 2022
    Inventors: Yu-Wen Cheng, Cheng-Tung Lin, Chih-Wei Chang, Hong-Mao Lee, Ming-Hsing Tsai, Sheng-Hsuan Lin, Wei-Jung Lin, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Wei-Yip Loh, Ya-Yi Cheng
  • Publication number: 20220293474
    Abstract: A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 15, 2022
    Inventors: Wei-Yip Loh, Yan-Ming Tsai, Hung-Hsu Chen, Chih-Wei Chang, Sheng-Hsuan Lin
  • Publication number: 20220278199
    Abstract: A device includes a fin extending from a semiconductor substrate, a gate stack over and along a sidewall of the fin, an isolation region surrounding the gate stack, an epitaxial source/drain region in the fin and adjacent the gate stack, and a source/drain contact extending through the isolation region, including a first silicide region in the epitaxial source/drain region, the first silicide region including NiSi2, a second silicide region on the first silicide region, the second silicide region including TiSix, and a conductive material on the second silicide region.
    Type: Application
    Filed: May 16, 2022
    Publication date: September 1, 2022
    Inventors: Yan-Ming Tsai, Chih-Wei Chang, Ming-Hsing Tsai, Sheng-Hsuan Lin, Hung-Hsu Chen, Wei-Yip Loh
  • Publication number: 20220277997
    Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 1, 2022
    Inventors: Ching-Yi Chen, Sheng-Hsuan Lin, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang
  • Patent number: 11411094
    Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Wen Cheng, Cheng-Tung Lin, Chih-Wei Chang, Hong-Mao Lee, Ming-Hsing Tsai, Sheng-Hsuan Lin, Wei-Jung Lin, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Wei-Yip Loh, Ya-Yi Cheng
  • Patent number: 11348839
    Abstract: A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yip Loh, Yan-Ming Tsai, Hung-Hsu Chen, Chih-Wei Chang, Sheng-Hsuan Lin