Patents by Inventor Sheng-Hsuan Lin

Sheng-Hsuan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170200800
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack, a spacer layer, and a dielectric layer over a substrate. The method includes removing a first portion of the dielectric layer to form a first hole in the dielectric layer. A second portion of the dielectric layer is under the first hole. The method includes forming a first protection layer over the gate stack and the spacer layer. The method includes forming a second protection layer over the first protection layer. The second protection layer includes a metal compound material, and the first protection layer and the second protection layer includes a same metal element. The method includes removing the second portion of the dielectric layer to form a through hole. The method includes forming a conductive contact structure in the through hole.
    Type: Application
    Filed: January 7, 2016
    Publication date: July 13, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Ping LIU, Hung-Chang HSU, Hung-Wen SU, Ming-Hsing TSAI, Rueijer LIN, Sheng-Hsuan LIN, Ya-Lien LEE, Yen-Shou KAO
  • Publication number: 20170170292
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first gate stack over a substrate. The first gate stack includes a gate electrode, a first hard mask (HM) disposed over the gate electrode, and sidewall spacers along sidewalls of the first gate stack. The method also includes forming a first dielectric layer over the first gate stack, forming a second HM over the first HM and top surfaces of sidewall spacers, forming a second dielectric layer over the second HM and the first dielectric layer and removing the second and first dielectric layers to form a trench to expose a portion of the substrate while the second HM is disposed over the first gate stack.
    Type: Application
    Filed: December 15, 2015
    Publication date: June 15, 2017
    Inventors: Hsiao-Ping Liu, Hung-Chang Hsu, Hung-Wen Su, Ming-Hsing Tsai, Rueijer Lin, Sheng-Hsuan Lin, Syun-Ming Jang, Ya-Lien Lee, Yen-Shou Kao
  • Patent number: 9666438
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate. The metal plug has a contact bottom surface that is substantially convex. The substantially convex contact bottom surface has an increased contact area as compared to a contact bottom surface of a metal plug that is not substantially convex. The increased contact area decreases a resistance of the metal plug. The increased contact area requires a smaller deposition amount to form a metal plug seed layer of the metal plug than a semiconductor device with a smaller contact area. A smaller deposition amount reduces an overhang of the deposited metal plug seed layer material. A reduced overhang of the deposited metal plug seed layer material reduces pitting in a metal plug formed from the deposited metal plug seed layer material.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: May 30, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yu-Hung Lin, Chih-Wei Chang, Sheng-Hsuan Lin, You-Hua Chou
  • Patent number: 9620601
    Abstract: Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: April 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Publication number: 20170098576
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer.
    Type: Application
    Filed: December 15, 2016
    Publication date: April 6, 2017
    Inventors: Yu-Hung Lin, You-Hua Chou, Sheng-Hsuan Lin, Chih-Wei Chang
  • Publication number: 20170004994
    Abstract: Disclosed herein is a method of forming a metal-to-semiconductor contact with a doped metal oxide interlayer. An insulating layer is formed on a top surface of a semiconductor substrate with target region at the top surface of the semiconductor substrate. An opening is etched through the insulating layer with the opening exposing a top surface of a portion of the target region. A doped metal oxide interlayer is formed in the opening and contacts the top surface of the target region. The remainder of the opening is filled with a metal plug, the doped metal oxide interlayer disposed between the metal plug and the substrate. The doped metal oxide interlayer is formed from one of tin oxide, titanium oxide or zinc oxide and is doped with fluorine.
    Type: Application
    Filed: September 14, 2016
    Publication date: January 5, 2017
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou
  • Patent number: 9530736
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou
  • Publication number: 20160365343
    Abstract: A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a gate structure over a substrate and forming a spacer on a sidewall of the gate structure. The method for manufacturing a semiconductor structure further includes forming a hard mask structure on a top surface of the gate structure and on an upper portion of the spacer but not on a bottom portion of the spacer.
    Type: Application
    Filed: June 15, 2015
    Publication date: December 15, 2016
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yu-Hung LIN, Hon-Lin HUANG, Rueijer LIN, Shih-Chi LIN, Sheng-Hsuan LIN
  • Publication number: 20160314979
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate. The metal plug has a contact bottom surface that is substantially convex. The substantially convex contact bottom surface has an increased contact area as compared to a contact bottom surface of a metal plug that is not substantially convex. The increased contact area decreases a resistance of the metal plug. The increased contact area requires a smaller deposition amount to form a metal plug seed layer of the metal plug than a semiconductor device with a smaller contact area. A smaller deposition amount reduces an overhang of the deposited metal plug seed layer material. A reduced overhang of the deposited metal plug seed layer material reduces pitting in a metal plug formed from the deposited metal plug seed layer material.
    Type: Application
    Filed: July 7, 2016
    Publication date: October 27, 2016
    Inventors: Yu-Hung Lin, Chih-Wei Chang, Sheng-Hsuan Lin, You-Hua Chou
  • Patent number: 9466488
    Abstract: Disclosed herein is a method of forming a metal-to-semiconductor contact with a doped metal oxide interlayer. An insulating layer is formed on a top surface of a semiconductor substrate with target region at the top surface of the semiconductor substrate. An opening is etched through the insulating layer with the opening exposing a top surface of a portion of the target region. A doped metal oxide interlayer is formed in the opening and contacts the top surface of the target region. The remainder of the opening is filled with a metal plug, the doped metal oxide interlayer disposed between the metal plug and the substrate. The doped metal oxide interlayer is formed from one of tin oxide, titanium oxide or zinc oxide and is doped with fluorine.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: October 11, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou
  • Publication number: 20160260633
    Abstract: An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.
    Type: Application
    Filed: May 17, 2016
    Publication date: September 8, 2016
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Patent number: 9397040
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate. The metal plug has a contact bottom surface that is substantially convex. The substantially convex contact bottom surface has an increased contact area as compared to a contact bottom surface of a metal plug that is not substantially convex. The increased contact area decreases a resistance of the metal plug. The increased contact area requires a smaller deposition amount to form a metal plug seed layer of the metal plug than a semiconductor device with a smaller contact area. A smaller deposition amount reduces an overhang of the deposited metal plug seed layer material. A reduced overhang of the deposited metal plug seed layer material reduces pitting in a metal plug formed from the deposited metal plug seed layer material.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: July 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou
  • Patent number: 9368357
    Abstract: A method includes etching a dielectric layer to form an opening, with an underlying region underlying the dielectric layer exposed to the opening, and performing a bombardment to bombard a surface region of the underlying region through the opening. After the bombardment, the surface region is reacted with a process gas to form a reaction layer. An anneal is then performed to remove the reaction layer.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: June 14, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Chang, Hung-Chang Hsu, Chun-Hsien Huang, Yu-Hung Lin, Li-Wei Chu, Sheng-Hsuan Lin, Wei-Jung Lin, Yu-Shiuan Wang
  • Publication number: 20160126102
    Abstract: A method includes etching a dielectric layer to form an opening, with an underlying region underlying the dielectric layer exposed to the opening, and performing a bombardment to bombard a surface region of the underlying region through the opening. After the bombardment, the surface region is reacted with a process gas to form a reaction layer. An anneal is then performed to remove the reaction layer.
    Type: Application
    Filed: December 29, 2015
    Publication date: May 5, 2016
    Inventors: Chih-Wei Chang, Hung-Chang Hsu, Chun-Hsien Huang, Yu-Hung Lin, Li-Wei Chu, Sheng-Hsuan Lin, Wei-Jung Lin, Yu-Shiuan Wang
  • Publication number: 20160043035
    Abstract: Contact structures and methods of forming contacts structures are contemplated by this disclosure. A structure includes a dielectric layer over a substrate, an adhesion layer, a silicide, a barrier layer, and a conductive material. The dielectric layer has an opening to a surface of the substrate. The adhesion layer is along sidewalls of the opening. The silicide is on the surface of the substrate. The barrier layer is on the adhesion layer and the silicide, and the barrier layer directly adjoins the silicide. The conductive material is on the barrier layer in the opening.
    Type: Application
    Filed: November 4, 2014
    Publication date: February 11, 2016
    Inventors: Yu-Hung Lin, Mei-Hui Fu, Sheng-Hsuan Lin
  • Publication number: 20160005824
    Abstract: Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.
    Type: Application
    Filed: July 1, 2014
    Publication date: January 7, 2016
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Patent number: 9230795
    Abstract: A method includes etching a dielectric layer to form an opening, with an underlying region underlying the dielectric layer exposed to the opening, and performing a bombardment to bombard a surface region of the underlying region through the opening. After the bombardment, the surface region is reacted with a process gas to form a reaction layer. An anneal is then performed to remove the reaction layer.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: January 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Shiuan Wang, Hung-Chang Hsu, Li-Wei Chu, Sheng-Hsuan Lin, Chun-Hsien Huang, Yu-Hung Lin, Chih-Wei Chang, Wei-Jung Lin
  • Publication number: 20150325484
    Abstract: Disclosed herein is a method of forming a metal-to-semiconductor contact with a doped metal oxide interlayer. An insulating layer is formed on a top surface of a semiconductor substrate with target region at the top surface of the semiconductor substrate. An opening is etched through the insulating layer with the opening exposing a top surface of a portion of the target region. A doped metal oxide interlayer is formed in the opening and contacts the top surface of the target region. The remainder of the opening is filled with a metal plug, the doped metal oxide interlayer disposed between the metal plug and the substrate. The doped metal oxide interlayer is formed from one of tin oxide, titanium oxide or zinc oxide and is doped with fluorine.
    Type: Application
    Filed: May 9, 2014
    Publication date: November 12, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou
  • Publication number: 20150318243
    Abstract: An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.
    Type: Application
    Filed: June 24, 2014
    Publication date: November 5, 2015
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Publication number: 20150311150
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.
    Type: Application
    Filed: April 25, 2014
    Publication date: October 29, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou