Abstract: A method for forming a semiconductor device and a semiconductor device are disclosed. The method includes: forming a stacked chip assembly, and at least one of the stacked chip assembly is bonded to a surface of a package wafer by chip-to-wafer bonding; obtaining a first reconstructed wafer by performing wafer reconstruction through forming a first filling cap layer over surfaces of the package wafer and the stacked chip assembly(ies) on the package wafer. With this method, stacked chip assembly with chip-level dimension can be stacked with a package wafer with wafer-level dimension, thus enabling dense stacking of chips. In addition, other stacked chip assembly(ies) can be bonded to the first reconstructed wafer by chip-to-wafer bonding, resulting in even denser stacking of chips and high process efficiency and helping in reducing the process cost and shortening the manufacturing time. The semiconductor device can be fabricated using the method.

Abstract: An image sensor structure and a method of fabricating the structure are disclosed, in image sensor structure, at least one die is bonded to pixel substrate by bonding first bonding layer to second bonding layer, and the die includes signal processing circuit and/or storage device for photosensitive elements in pixel substrate. The die is bonded to the pixel substrate so that the signal processing circuit and/or storage device is/are coupled to photosensitive elements in pixel substrate. In this way, signal processing and/or storage functions of the image sensor can be provided without additional occupation of the area of the pixel substrate, allowing for more photosensitive elements to be arranged on the pixel substrate with the same area and thus resulting in a larger photosensitive area. Moreover, less wiring is needed on the 2D plane of the pixel substrate, helping in reducing interference with signals and delays and improving imaging quality.

Abstract: Disclosed are a polyethylene glycol conjugate drug, and a preparation method therefor and the use thereof. Specifically, the present invention relates to a polyethylene glycol conjugate drug represented by formula A or a pharmaceutically acceptable salt thereof, a method for preparing the polyethylene glycol conjugate drug or the pharmaceutically acceptable salt thereof, an intermediate for preparing the polyethylene glycol conjugate drug or the pharmaceutically acceptable salt thereof, a pharmaceutical composition comprising the polyethylene glycol conjugate drug or the pharmaceutically acceptable salt thereof, and the use of the polyethylene glycol conjugate drug or the pharmaceutically acceptable salt thereof in the preparation of a drug.

Abstract: The present invention relates to the technical field of acetonitrile refining, and in particular, to an improved acetonitrile purification process for an ultrahigh performance liquid chromatography-mass spectrometer. The present invention provides an acetonitrile purification process. A high-purity finished product may be obtained by performing operations of oxidation, rectification adsorption, drying, reflux rectification and filtration on industrial acetonitrile and controlling related parameters such as temperature, flow and the like, continuous production is ensured, a light transmittance of the finished product in ultraviolet rays of 200 to 260 nm is greater than or equal to 95%, water and impurities in the industrial acetonitrile are removed, and the requirements of the ultrahigh performance liquid chromatography-mass spectrometer are met; moreover, by controlling process parameters and equipment.

Abstract: The present disclosure provides a chip packaging method and a chip packaging structure. The chip packaging method includes: providing an encapsulated grain and a packaging substrate, the encapsulated grain including a first hybrid bonding structure; wherein the packaging substrate includes a front side and a back side opposite to each other; a second hybrid bonding structure is formed on the front side of the packaging substrate and a connection pin is formed on the back side of the packing substrate; the second hybrid bonding structure and the connection pin are electrically connected through a third connecting metal column penetrating the packaging substrate; and bonding together the first hybrid bonding structure of the encapsulated grain and the second hybrid bonding structure of the packaging substrate by medium-to-medium and metal-to-metal aligned bonding such that the encapsulated grain is bonded to the packaging substrate.

Abstract: An HOD device, comprising: a framework; covering material, covering the frame work; at least one conductive region, provided on or in the covering material; wherein the conductive region is coupled to a capacitance detection circuit or a predetermined voltage level. The HOD device can be a vehicle control device such as a steering wheel. The conductive region comprises conductive wires which can be threads of the covering material. By this way, the arrangements of the conductive wires can be changed corresponding to the size or the shape of the frame work or any other requirements. Also, the interference caused by unstable factors can be improved since the conductive wires can be coupled to a ground source of the vehicle to provide a short capacitance sensing path.

Abstract: A key-value store and a file system are integrated together to provide improved operations. The key-value store can include a log engine, a hash engine, a sorting engine, and a garbage collection manager. The features of the key-value store can be configured to reduce the number of I/O operations involving the file system, thereby improving read efficiency, reducing write latency, and reducing write amplification issues inherent in the combined key-value store and file system.

Abstract: A semiconductor device includes a first wafer; a trench isolation ring formed in the first wafer and comprising a first metal layer; a first insulating dielectric layer formed on a surface of the first wafer, including at least one first through hole and at least one second through hole formed therein, the first through hole exposing a surface of the first metal layer, the second through hole exposing the surface of the first wafer; a barrier layer formed at least on the surface of the first wafer exposed in the second through hole; and a second metal layer formed on the first insulating dielectric layer so as to fill up the first and second through holes. The semiconductor device circumvent increased contact resistance, possible aluminum spiking and other problems. The method exhibits improved robustness and imparts higher performance to a semiconductor device fabricated using the method.

Abstract: A three-dimensional (3D) integrated circuit (IC) module and a method of fabricating the 3D IC module are disclosed. In the 3D IC module, a conductive hole for connection with an internal specified metal layer and a trench arranged to avoid the conductive hole are formed in a topmost substrate of a semiconductor structure. A first passivation layer spans over and covers the trench, the first passivation layer and the trench together delimit a heat exchange channel. During operation of 3D IC module, a heat dissipation medium may be caused to flow through the heat exchange channel to facilitate heat dissipation. Thus, the 3D IC module has enhanced heat dissipation ability and is substantially immune from the problems of excessive heat build-up and uneven heat dissipation. This helps optimize performance and reliability of the 3D IC module. The method can be used to make such a 3D IC module.

Abstract: A backside illuminated (BSI) image sensor substrate and a method of manufacturing a BSI image sensor are disclosed. A first nitride layer (9) is formed on a metal material layer (70), and a first dry etching process is then performed on both the first nitride layer (9) and the metal material layer (70). In this way, during the etching of the metal material layer (70), the first nitride layer (9) is bombarded so that nitrogen atoms or nitrogen ions escape from the first nitride layer (9), during the formation of a metal grid layer (7), the escaping nitrogen atoms or nitrogen ions react with the metal on sidewalls of second openings (7a), forming a metal nitride layer which protects the metal grid at the sidewalls of the second openings (7a) from being damaged. As such, the resulting metal grid layer (7) has smooth sidewalls and good morphology.

Abstract: A particles capturing system includes a venturi filter device, a cyclone filter device, a plurality of first nozzles and air to flow through the system. The venturi filter device has an air intake portion, a neck portion and an air outlet portion. The cyclone filter device, disposed in the air outlet portion, has an entrance and an exit. The plurality of first nozzles, disposed inside the venturi filter device, have a height greater than that of the the neck portion. When the air flows, the air enters the venturi filter device via an air inlet of the air intake portion, then orderly passes through the neck portion and the plurality of first nozzles, then enters the cyclone filter device via the entrance, and finally leaves the cyclone filter device via the exit, such that particles in the flowing air can be captured.

Abstract: A method of handling a test pad and a method of fabricating a semiconductor device are disclosed. The method of handling a test pad includes: providing a substrate formed thereon with a first insulating dielectric layer and a first test pad in the first insulating dielectric layer, wherein a surface of the first test pad is at least partially exposed from the first insulating dielectric layer, and there is a probe mark with a protrusion resulting from testing with probe tips on the surface portion of the first test pad exposed from the first insulating dielectric layer; and heating and melting the protrusion by laser annealing, thereby reducing a height of the protrusion. This invention can ensure good flatness of a surface to be bonded while enabling reduced process complexity and preventing metal contamination of the surface to be bonded.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate defining a pixel area; a trench fill structure formed in the substrate in the pixel area; a buffer dielectric layer formed over a surface of the substrate in the pixel area, the buffer dielectric layer defining a first opening, which at least exposes a portion of the substrate surrounding the trench fill structure; and a metal grid layer formed on the buffer dielectric layer, the metal grid layer filling the first opening to at least directly contact with and electrically connect to the exposed portion of the substrate. The present invention provides a technical solution that brings the metal grid layer into electrical connection with the exposed portion of the substrate, thus allowing optimization or amelioration of the semiconductor device's electrical performance.

Abstract: A method of fabricating of semiconductor device is disclosed. The method of fabricating semiconductor device includes: forming a trench fill structure in a substrate in a pixel area; covering a buffer dielectric layer over a surface of the substrate in the pixel area, the buffer dielectric layer burying the trench fill structure; etching the buffer dielectric layer to form a first opening, which at least exposes a portion of the substrate surrounding a top surface of the trench fill structure; and forming a metal grid layer on the buffer dielectric layer, wherein the metal grid layer fills the first opening to at least directly contact with and electrically connect to the exposed portion of the substrate. The present invention provides a technical solution that brings the metal grid layer into electrical connection with the exposed portion of the substrate, thus allowing optimization or amelioration of the semiconductor device's electrical performance.

Abstract: A method of fabricating an IC device is disclosed, in which a dielectric layer is first etched to form a contact opening and a dummy opening. Both do not extend through the dielectric layer, the contact opening has a width greater than that of the dummy opening. A sacrificial layer, which covers inner surface of the dummy opening and the dielectric layer at side surface of the contact opening, and from which the dielectric layer at bottom surface of the contact opening is exposed, is then formed, and under protection of this sacrificial layer, the dielectric layer exposed in the contact opening is etched in a self-aligned manner, a self-aligned contact hole is formed, in which a surface of the conductive structure is exposed. In this way, reliability of a contact that extends in both contact opening and self-aligned contact hole is ensured, avoiding the problem of possible contact failure.

Abstract: The present disclosure describes a semiconductor structure with a metal ion capture layer and a method for forming the structure. The method includes forming a first fin structure and a second fin structure on a substrate and forming a first gate structure over the first fin structure and a second gate structure over the second fin structure, where the first gate structure adjoins the second gate structure. The method further includes forming a dielectric layer on the first and second gate structures, removing a portion of the dielectric layer above an adjoining portion of the first and second gate structures to form an opening, and forming a metal ion capture layer in the opening.

Abstract: A method of design for matching of wafers, a wafer bonding structure and a chip bonding structure includes: providing a first wafer including unit arrays that each include at least two first dies; providing a second wafer including second dies that each cover at least one of the unit arrays, and the second dies matched in terms of performance with the first dies in the unit arrays that it covers. The first and second wafers are provided with corresponding alignment marks. With this application, two or more wafers with corresponding dies differing considerably in terms of shape or area can be designed to match each other and become suitable to be bonded together. This enables effective area utilization of, and better matching in terms of area and performance between, the dies, greatly shortens the development time of new products and adds great diversity and freedom to product design.

Abstract: A semiconductor device and a method of fabricating thereof are disclosed. The method of fabricating a semiconductor device includes: forming a trench fill structure in a substrate in a pixel area; covering a buffer dielectric layer over a surface of the substrate in the pixel area, the buffer dielectric layer burying the trench fill structure; etching the buffer dielectric layer to form a first opening, which exposes at least a portion of the substrate surrounding sidewalls of a top of the trench fill structure and/or at least a portion of the top of the trench fill structure; and forming a metal grid layer on the buffer dielectric layer, wherein the metal grid layer fills the first opening and is electrically connected to the exposed portion of the substrate and/or the exposed portion of the trench fill structure.

Abstract: A semiconductor device and a method of fabricating the same are disclosed. A reference direction for a substrate is parallel to a first or second crystallographic direction, and a patterned hard mask layer is distributed along the first crystallographic direction. For substrates with notches oriented in different crystallographic directions, the patterned mask layer may be used as a mask for forming trenches in the substrate surface. When viewed normal to a cross-section perpendicular to the substrate, each trench has a cross-sectional width decreasing from the substrate surface toward the inside of the substrate. This allows the semiconductor device to have increased light absorption and conversion efficiency. Forming the trenches by wet etching can avoid increased dark current due to damage to the trenches’ side surfaces that may be caused by the use of a dry etching process. Thus, an effective improvement in terms of dark current can be achieved.