Abstract: A semiconductor device and a method of fabricating the same are disclosed. A reference direction for a substrate is parallel to a first or second crystallographic direction, and a patterned hard mask layer is distributed along the first crystallographic direction. For substrates with notches oriented in different crystallographic directions, the patterned mask layer may be used as a mask for forming trenches in the substrate surface. When viewed normal to a cross-section perpendicular to the substrate, each trench has a cross-sectional width decreasing from the substrate surface toward the inside of the substrate. This allows the semiconductor device to have increased light absorption and conversion efficiency. Forming the trenches by wet etching can avoid increased dark current due to damage to the trenches’ side surfaces that may be caused by the use of a dry etching process. Thus, an effective improvement in terms of dark current can be achieved.

Abstract: A high electron mobility transistor (HEMT) device includes at least an AlN nucleation layer, a superlattice composite layer, a GaN electron transport layer, and an AlGaN barrier layer. The superlattice composite layer is disposed on the AlN nucleation layer, and the superlattice composite layer includes a plurality of AlN films and a plurality of GaN films stacked alternately to reduce device stress. The GaN electron transport layer is disposed on the superlattice composite layer, and the AlGaN barrier layer is disposed on the GaN electron transport layer.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The manufacturing method of a semiconductor device, comprising following steps: providing a substrate and sequentially forming a first mask layer and a second mask layer on the substrate, wherein the second mask layer covers the first mask layer; dry etching the first mask layer using the second mask layer as a mask, wherein the first mask layer has a patterned first opening; and removing the second mask layer and wet etching the substrate using the patterned first mask layer as a mask to form a plurality of trenches on the substrate, wherein the plurality of trenches extend from a surface of the substrate to inside of the substrate, and a cross-sectional width in a cross-section perpendicular to the substrate of the plurality of trenches gradually decreases from the surface of the substrate to the inside of the substrate.

Abstract: Single cell ribonucleic acid sequencing data has provided numerous avenues to monitor and study organism more thoroughly at a cellular level, including spatial arrangement of cells. An approach to predicting cellular immune response based on cellular spatial features may be presented herein. The approach may include utilizing ribonucleic acid sequence data for a single cell (“scRNA-seq”) or cell from a tissue. The approach may also include extracting spatial features of the single cell using the scRNA-seq data including cell-to-cell interactions and relative distance between cells. The approach may include predicting an immune response of a cell or cells based on the extracted spatial features.

Abstract: An optical sensing circuit and an optical sensing method are provided. The optical sensing circuit includes a first photosensitive unit, a second photosensitive unit, an arithmetic unit, and a control unit. The first photosensitive unit and the second photosensitive unit provide a sensing current during a light sensing period. The arithmetic unit generates a combined current according to the sensing current during the light sensing period. The control unit generates a first sensed value and a second sensed value according to the combined current.

Abstract: A bonding structure and a manufacturing method therefor. A first hybrid bonding structure is formed on a first wafer; an interconnection structure and a second hybrid bonding structure are formed on the front surface of a second wafer. The first wafer and the second wafer are bonded by means of the first hybrid bonding structure and the second hybrid bonding structure, a gasket electrically connected to the interconnection structure is formed on the back surface of the second wafer, and the interconnection structure below the gasket and a second conductive bonding pad in the second hybrid bonding structure are provided in a staggered manner in the horizontal direction. According to the solution, the interconnection structure and the second conductive bonding pad are arranged in a staggered manner, so that recesses generated by structural stacking are avoided, and device failure caused by the recesses is further avoided.

Abstract: An optical sensing apparatus is provided. A bias-voltage generating circuit provides a first bias voltage and a second bias voltage to a photo-sensing diode when the optical sensing apparatus is respectively in a first mode and a second mode, such that the photo-sensing diode provides a time-of-flight ranging signal in the first mode and an ambient-light sensing signal in the second mode. A quenching circuit provides the time-of-flight ranging signal to a ranging signal processing circuit in the first mode, quenches the photo-sensing diode, and provides the ambient-light sensing signal to a light-sensing signal processing circuit in the second mode.

Abstract: A method of fabricating an IC device is disclosed, in which a dielectric layer is first etched to form a contact opening and a dummy opening. Both do not extend through the dielectric layer, the contact opening has a width greater than that of the dummy opening. A sacrificial layer, which covers inner surface of the dummy opening and the dielectric layer at side surface of the contact opening, and from which the dielectric layer at bottom surface of the contact opening is exposed, is then formed, and under protection of this sacrificial layer, the dielectric layer exposed in the contact opening is etched in a self-aligned manner, a self-aligned contact hole is formed, in which a surface of the conductive structure is exposed. In this way, reliability of a contact that extends in both contact opening and self-aligned contact hole is ensured, avoiding the problem of possible contact failure.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes: providing a device wafer and a carrier wafer, the device wafer including an SOI substrate comprising, stacked from the bottom upward, a lower substrate, a buried insulator layer and a semiconductor layer; bonding the device wafer at a front side thereof to the carrier wafer; removing at least the lower substrate through thinning the device wafer from a backside thereof, wherein the backside of the device wafer opposes the front side thereof; and providing a high-resistance substrate and bonding the device wafer at the backside thereof to the high-resistance substrate, the high-resistance substrate having a resistivity higher than that of the lower substrate. With the present disclosure, lower signal loss and improved signal linearity can be achieved while avoiding a significant cost increase.

Abstract: A localization and attitude estimation method using magnetic fields includes the following steps. First, in three-dimensional coordinates, at least three magnetic landmarks arbitrarily disposed around a moving carrier are selected, wherein any two of the at least three magnetic landmarks have different magnetic directions. One set of at least five tri-axes magnetic sensors is used to sense the magnetic fields of the at least three magnetic landmarks. Three magnetic components on three axes of a current position of each of the tri-axes magnetic sensors are respectively generated by a demagnetization method. Five non-linear magnetic equations are solved to obtain position information and magnetic moment information of the at least three magnetic landmarks in the three-dimensional coordinates. Position vectors and attitude vectors of the set of at least five tri-axes magnetic sensors in a three-dimensional space are estimated based on tri-axes magnetic moment vectors of the magnetic landmarks.

Abstract: The present invention provides a large die, a method of forming the large die and a large die wafer. The method includes: providing a wafer containing a plurality of large dies each having a size greater than that of a maximum field of exposure of a stepper, each large die including at least two die portions to be stitched together, the die portions including a substrate and a first metal layer, the first metal layer including at least to-be-interconnected metal layers for interconnection of the die portions; and forming a second metal layer including at least inter-die interconnecting metal layers crossing dummy dicing margins between adjacent die portions and coming into electrical connection with the to-be-interconnected metal layers of the adjacent die portions. The present invention allows interconnection of the die portions to be stitched together in each large die.

Abstract: A pixel circuit includes: pixel units, wherein each pixel unit includes a light-emitting element and a pixel driving circuit, the pixel driving circuit and the light-emitting element are electrically connected to a first node; a first compensation sub-circuit electrically connected to each pixel driving circuit, and configured to provide an initialization signal to the pixel driving circuit, obtain a voltage at the first node when the light-emitting element emits light via the pixel driving circuit, and generate a compensation data signal based on the voltage at the first node; and a second compensation sub-circuit electrically connected to each pixel driving circuit and configured to keep the voltage at the first node within a set operating voltage range of the light-emitting element. The pixel driving circuit is further configured to initialize the first node based on the initialization signal, and use the compensation data signal to drive the light-emitting element.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The method includes: forming a trench fill structure in a pixel region of a substrate; covering a surface of the substrate in the pixel region with a buffer dielectric layer; etching the buffer dielectric layer to form a first opening exposing at least part of the substrate around a top side wall portion of the trench fill structure and/or at least a top portion of the trench fill structure; filling a first conductive metal layer in the first opening in such a manner that it is electrically connected to the exposed part of the substrate and/or the exposed portion of the trench fill structure; and forming a metal grid layer on the buffer dielectric layer so that it is electrically connected to the first conductive metal layer.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The method of manufacturing the semiconductor device includes: forming a trench fill structure in a pixel region of a substrate, where a high-k dielectric layer is sandwiched between a side wall of a fill material in the trench fill structure and the substrate; forming a plug structure in a pad region of the substrate; covering a surface of the substrate in the pixel region and the pad region with a buffer dielectric layer; etching the buffer dielectric layer to form first opening exposing at least part of the substrate around a top side wall portion of the trench fill structure and/or at least a top portion of the trench fill structure; and forming a metal grid layer on the buffer dielectric layer in the pixel region.

Abstract: The present invention discloses a ?-transaminase mutant obtained through DNA synthetic shuffling combined mutation. The ?-transaminase mutant is obtained through point mutation of a wild type ?-transaminase from Aspergillus terrus. The amino acid sequence of the wild type ?-transaminase is shown in SEQ ID NO: 1. The mutation site of the ?-transaminase mutant is any one of: (1) F115L-H210N-M150C-M280C; (2) F115L-H210N; (3) F115L-H210N-E253A-I295V; (4) I77L-F115L-E133A-H210N-N245D; (5) I77L-Q97E-F115L-L118T-E253A-G292D; (6) I77L-E133A-N245D-G292D; and (7) H210N-N245D-E253A-G292D. According to the present invention, forward mutations obtained in the previous stage are randomly combined through a DNA synthetic shuffling combined mutation method.

Abstract: An industrial image inspection method includes: generating a test latent vector of a test image; measuring a distance between a training latent vector of a normal image and the test latent vector of the test image; and judging whether the test image is normal or defected according to the distance between the training latent vector of the normal image and the test latent vector of the test image.

Abstract: Compositions, systems, and methods for producing nanoalloys and/or nanocomposites using tandem laser ablation synthesis in solution-galvanic replacement reaction (LASiS-GRR) are disclosed. The method may include disposing a first metal composition within a reaction cell, adding a quantity of a second metal composition into the reaction cell, ablating, with a laser, the first metal composition disposed in the quantity of the second metal composition within the reaction cell, and tuning one or more reaction parameter and/or one or more functional parameter during the tandem LASiS-GRR in order to tailor at least one characteristic of the metal nanoalloy and/or the metal nanocomposite.

Abstract: A pixel circuit includes: pixel units, wherein each pixel unit includes a light-emitting element and a pixel driving circuit, the pixel driving circuit and the light-emitting element are electrically connected to a first node; a first compensation sub-circuit electrically connected to each pixel driving circuit, and configured to provide an initialization signal to the pixel driving circuit, obtain a voltage at the first node when the light-emitting element emits light via the pixel driving circuit, and generate a compensation data signal based on the voltage at the first node; and a second compensation sub-circuit electrically connected to each pixel driving circuit and configured to keep the voltage at the first node within a set operating voltage range of the light-emitting element. The pixel driving circuit is further configured to initialize the first node based on the initialization signal, and use the compensation data signal to drive the light-emitting element.

Abstract: A particles capturing system includes a venturi filter device, a cyclone filter device, a plurality of first nozzles and air to flow through the system. The venturi filter device has an air intake portion, a neck portion and an air outlet portion. The cyclone filter device, disposed in the air outlet portion, has an entrance and an exit. The plurality of first nozzles, disposed inside the venturi filter device, have a height greater than that of the the neck portion. When the air flows, the air enters the venturi filter device via an air inlet of the air intake portion, then orderly passes through the neck portion and the plurality of first nozzles, then enters the cyclone filter device via the entrance, and finally leaves the cyclone filter device via the exit, such that particles in the flowing air can be captured.