Abstract: A centrifugal heat dissipation fan including a housing and an impeller is provided. The housing has at least one inlet disposed along an axis and at least one first outlet and a second outlet located in different radial directions, wherein the first outlet and the second outlet are opposite to and separated from each other. The impeller is disposed in the housing along the axis. A heat dissipation system of an electronic device is also provided.

Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.

Abstract: Various embodiments of the teachings herein include an image processing system comprising: a video stream processing device configured to receive a video stream, segment the video stream into multiple frames of pictures arranged in chronological order, and distribute the multiple frames of pictures to edge computing devices in a connected edge computing device group; and a picture collecting device configured to receive pictures from the edge computing device group. The individual edge computing devices in the edge computing device group are each configured to subject the received pictures to target identification, and send the pictures marked with a region in which an identified target is located. The picture collecting device is further configured to restore in chronological order as a video stream the received pictures marked with target identification results.

Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.

Abstract: A data analysis system is provided in the invention. The data analysis system includes a storage device, a field-data-description-file generating module, and a general data readiness analysis module. The storage device stores a plurality of raw data. The field-data-description-file generating module generates the field-data-description files corresponding to the raw data. The general data readiness analysis module obtains a score of the consistency indicator of the raw data according to the field-data-description files. The general data readiness analysis module obtains the data of the category which needs to be analyzed from the raw data according to the category of each field-data-description file. The general data analysis module obtains the score of the completeness indicator, the score of the accuracy indicator, the score of the validity indicator, and the score of the compaction indicator which all correspond to the data of the category which needs to be analyzed.

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

Abstract: A full load test system of an electrical power converter and the test method thereof is disclosed. The full load test method of the electrical power converter comprises the following steps: (a) providing a power converter under test (PCUT); (b) configuring the PCUT in/on a test circuit; (c) serially connecting the PCUT with at least one bidirectional power converter in the test circuit; (d) connecting the test circuit to an alternating current low voltage three-phase power source; and (e) performing a test of the PCUT under full-load condition.

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

Abstract: The present invention discloses a vessel power safety control system and operating method thereof. The vessel power safety control system includes a load power management module, a real-time monitoring module, an integration module and a power module. The present invention can assist the autonomous ship as any occurrence of fault during navigation. Once the accident occurs, the load power management module will give an instruction to control the DC bus to switch from closed circuit to open circuit to protect other equipment. After determining whether the errors of the equipment on board is eliminated, the load power management system performs automatic system reset procedure. As such, the DC bus can be converted from an open circuit to a closed circuit to restart the power supply for the facility.

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

Abstract: A data analysis system is provided in the invention. The data analysis system includes a storage device, a field-data-description-file generating module, and a general data readiness analysis module. The storage device stores a plurality of raw data. The field-data-description-file generating module generates the field-data-description files corresponding to the raw data. The general data readiness analysis module obtains a score of the consistency indicator of the raw data according to the field-data-description files. The general data readiness analysis module obtains the data of the category which needs to be analyzed from the raw data according to the category of each field-data-description file. The general data analysis module obtains the score of the completeness indicator, the score of the accuracy indicator, the score of the validity indicator, and the score of the compaction indicator which all correspond to the data of the category which needs to be analyzed.

Abstract: A full load test system of an electrical power converter and the test method thereof is disclosed. The full load test method of the electrical power converter comprises the following steps: (a) providing a power converter under test (PCUT); (b) configuring the PCUT in/on a test circuit; (c) serially connecting the PCUT with at least one bidirectional power converter in the test circuit; (d) connecting the test circuit to an alternating current low voltage three-phase power source; and (e) performing a test of the PCUT under full-load condition.

Abstract: An energy management strategy for boats and ships is provided. The aforementioned strategy comprises a strategy for low-load conditions and a strategy for high-load conditions, specifically for the sailing conditions of boats and ships. The output and distribution of energy are dynamically adjusted in accordance with commands, tides, time, locations, weather, hydrologic conditions and other factors may impact the sailing, in order to optimize the energy efficiency of boats and ships.

Abstract: A flip-flop circuit including a first logic circuit, a first master latch, a second master latch, and a slave latch is provided. The first logic circuit operates a logic operation on a selecting signal and a clock signal to generate a first control signal. The first master latch receives a data signal according to the first control signal and latches the data signal according to the selecting signal and the clock signal. The second master latch receives a scan data signal according to the selecting signal and the clock signal, wherein an output terminal of the second master latch is directly connected to an output terminal of the first master latch. The slave latch latches a signal on the output terminals of the first and second master latches for generating an output signal.

Abstract: A flip-flop circuit including a first logic circuit, a first master latch, a second master latch, and a slave latch is provided. The first logic circuit operates a logic operation on a selecting signal and a clock signal to generate a first control signal. The first master latch receives a data signal according to the first control signal and latches the data signal according to the selecting signal and the clock signal. The second master latch receives a scan data signal according to the selecting signal and the clock signal, wherein an output terminal of the second master latch is directly connected to an output terminal of the first master latch. The slave latch latches a signal on the output terminals of the first and second master latches for generating an output signal.