Patents by Inventor Sheng-Hua Chen
Sheng-Hua Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9641159Abstract: A flip-flop circuit including a first logic circuit, a first master latch, a second master latch, and a slave latch is provided. The first logic circuit operates a logic operation on a selecting signal and a clock signal to generate a first control signal. The first master latch receives a data signal according to the first control signal and latches the data signal according to the selecting signal and the clock signal. The second master latch receives a scan data signal according to the selecting signal and the clock signal, wherein an output terminal of the second master latch is directly connected to an output terminal of the first master latch. The slave latch latches a signal on the output terminals of the first and second master latches for generating an output signal.Type: GrantFiled: February 18, 2016Date of Patent: May 2, 2017Assignee: Faraday Technology Corp.Inventors: Chiang-Hsiang Liao, Sheng-Hua Chen
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Publication number: 20170087996Abstract: An energy management strategy for boats and ships is provided. The output and distribution of energy are dynamically adjusted in accordance with commands, tides, time, locations, weather, hydrologic conditions and other factors may impact the sailing, in order to optimize the energy efficiency of boats and ships.Type: ApplicationFiled: December 21, 2015Publication date: March 30, 2017Inventors: CHIH-HUNG LIN, HUNG-HSI LIN, SHENG-HUA CHEN, JEN-FU TSAI, HSIAO-YU HSU, SHEAN-KWANG CHOU, KAI-PING HSU
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Patent number: 9250295Abstract: The present invention relates to a high-voltage battery charging simulation system that includes a simulation high-voltage battery pack, a simulation battery management system, a multi-party communication device, and a charging station. The voltage of the simulation high-voltage battery pack can be calculated and updated immediately by the simulation battery management system to simulate the feature of real battery pack, so that it can detect the operation of the multi-party communication device and the charging station.Type: GrantFiled: July 19, 2012Date of Patent: February 2, 2016Assignee: SHIP AND OCEAN INDUSTRIES R&D CENTERInventors: Shean-Kwang Chou, Hung-Hsi Lin, Chih-Hung Lin, Sheng-Hua Chen
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Patent number: 8824172Abstract: An apparatus and method for a flyback power converter reduce the standby output voltage of the flyback power converter by switching the reference voltage provided by a shunt regulator of the flyback power converter or the ratio of voltage divider resistors of the shunt regulator, to reduce the standby power consumption by an output feedback circuit of the flyback power converter, the shunt regulator, and the voltage divider resistors, and thereby improve the power loss of the flyback power converter in standby mode.Type: GrantFiled: August 9, 2010Date of Patent: September 2, 2014Assignee: Richpower Microelectronics CorporationInventors: Sheng-Hua Chen, Tzu-Chen Lin, Pei-Lun Huang
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Publication number: 20130271065Abstract: The present invention relates to a high-voltage battery charging simulation system that includes a simulation high-voltage battery pack, a simulation battery management system, a multi-party communication device, and a charging station. The voltage of the simulation high-voltage battery pack can be calculated and updated immediately by the simulation battery management system to simulate the feature of real battery pack, so that it can detect the operation of the multi-party communication device and the charging station.Type: ApplicationFiled: July 19, 2012Publication date: October 17, 2013Applicant: Ship and Ocean Industries R&D CenterInventors: SHEAN-KWANG CHOU, Hung-Hsi Lin, Chih-Hung Lin, Sheng-Hua Chen
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Publication number: 20130229143Abstract: A multi-party communication control system and charge process of a DC charging system is provided. According battery pack information transmitted by a battery control system, a multi-party communication control device determines a charge current or a charge voltage and a voltage-controlled charge mode required by a battery pack. The multi-party communication control device then translates the charge voltage or the charge current to a CHAdeMO language that is next transmitted to a CHAdeMO charger.Type: ApplicationFiled: March 10, 2012Publication date: September 5, 2013Applicant: Ship and Ocean Industries R&D CenterInventors: SHEAN-KWANG CHOU, Ying-Chao Liao, Hung-Gsi Lin, Chih-Hung Lin, Sheng-Hua Chen, Hsiao-Yu Hsu, Ming-En Fang, Kai-Ping Hsu, Wen-Hua Pan
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Publication number: 20110051463Abstract: An apparatus and method for a flyback power converter reduce the standby output voltage of the flyback power converter by switching the reference voltage provided by a shunt regulator of the flyback power converter or the ratio of voltage divider resistors of the shunt regulator, to reduce the standby power consumption by an output feedback circuit of the flyback power converter, the shunt regulator, and the voltage divider resistors, and thereby the power loss of the flyback power converter in standby mode.Type: ApplicationFiled: August 9, 2010Publication date: March 3, 2011Applicant: RICHPOWER MICROELECTRONICS CORPORATIONInventors: SHENG-HUA CHEN, TZU-CHEN LIN, PEI-LUN HUANG
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Patent number: 7847611Abstract: A level shifter includes a Not gate coupled to a signal input and operable between a first high level and a low level; a first PMOS transistor coupled to a second voltage source and a control end; a first NMOS transistor coupled to the first PMOS transistor, a Not-gate output end and a reference voltage; and a control circuit coupled to the signal input, the Not-gate output end and the second voltage source. When the signal input and the Not-gate output end are at the first high level and the low level, respectively, the first PMOS transistor is turned on so that the signal output is at a second high level; and when the signal input and the Not-gate output end are switched contrarily, the first PMOS transistor is turned off and the signal output is at the low level.Type: GrantFiled: January 21, 2009Date of Patent: December 7, 2010Assignee: Faraday Technology Corp.Inventors: Chih-Wen Yang, Sheng-Hua Chen
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Patent number: 7764101Abstract: A Schmitt trigger includes A first PMOS transistors having the drains and sources thereof serially connected and coupled between a voltage source and an output end, and having gates thereof coupled to an input end; B first NMOS transistors having the drains and sources thereof serially connected and coupled between the output end and ground, and having gates thereof coupled to the input end; C second PMOS transistors, each being coupled between ground and a node between the drain and the source of the first PMOS transistors and having the gate thereof coupled to the output end; and D second NMOS transistors, each being coupled between the voltage source and a node between the drain and the source of the first NMOS transistors and having the gate thereof coupled to the output end. A is greater than 2 and C, and B is greater than 2 and D.Type: GrantFiled: January 22, 2009Date of Patent: July 27, 2010Assignee: Faraday Technology Corp.Inventors: Jeng-Huang Wu, Sheng-Hua Chen
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Publication number: 20090189670Abstract: A level shifter includes a Not gate coupled to a signal input and operable between a first high level and a low level; a first PMOS transistor coupled to a second voltage source and a control end; a first NMOS transistor coupled to the first PMOS transistor, a Not-gate output end and a reference voltage; and a control circuit coupled to the signal input, the Not-gate output end and the second voltage source. When the signal input and the Not-gate output end are at the first high level and the low level, respectively, the first PMOS transistor is turned on so that the signal output is at a second high level; and when the signal input and the Not-gate output end are switched contrarily, the first PMOS transistor is turned off and the signal output is at the low level.Type: ApplicationFiled: January 21, 2009Publication date: July 30, 2009Applicant: FARADAY TECHNOLOGY CORPORATIONInventors: CHIH-WEN YANG, SHENG-HUA CHEN
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Publication number: 20090189665Abstract: A Schmitt trigger includes A first PMOS transistors having the drains and sources thereof serially connected and coupled between a voltage source and an output end, and having gates thereof coupled to an input end; B first NMOS transistors having the drains and sources thereof serially connected and coupled between the output end and ground, and having gates thereof coupled to the input end; C second PMOS transistors, each being coupled between ground and a node between the drain and the source of the first PMOS transistors and having the gate thereof coupled to the output end; and D second NMOS transistors, each being coupled between the voltage source and a node between the drain and the source of the first NMOS transistors and having the gate thereof coupled to the output end. A is greater than 2 and C, and B is greater than 2 and D.Type: ApplicationFiled: January 22, 2009Publication date: July 30, 2009Applicant: FARADAY TECHNOLOGY CORPORATIONInventors: JENG-HUANG WU, SHENG-HUA CHEN
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Publication number: 20080231336Abstract: The present invention is a scan flip-flop circuit with extra hold time margin. The scan flip-flop circuit includes a multiplexer, a sense amplifier and a latch. The latch includes a generation unit for generating an output signal in response to a first signal and a second signal outputted from the sense amplifier, and a storage unit receives the second signal and the output signal and maintains the output signal of the latch when the first signal and the second signal are non-activated.Type: ApplicationFiled: March 17, 2008Publication date: September 25, 2008Applicant: FARADAY TECHNOLOGY CORPORATIONInventors: Jeng Huang WU, Sheng Hua Chen
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Publication number: 20080178135Abstract: Electronic cells/cell library and related technology/method capable of achieving high integration of integrated circuits. In one embodiment, the proposed technology adopts cells with cell heights equal to a non-integer multiplication of the routing track to establish a cell library, so a layout area of each cell is reduced. Further, higher integration of integrated circuit can be achieved by applying the proposed cells in integrated circuits.Type: ApplicationFiled: July 27, 2007Publication date: July 24, 2008Applicant: FARADAY TECHNOLOGY CORPORATIONInventors: Jeng-Huang Wu, Sheng-Hua Chen, Meng-Jer Wey
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Patent number: 7057468Abstract: A CMOS Pierce crystal oscillator. A clock generator with activation control, for generating a clock signal. The clock generator comprises an amplifier, a shaping circuit and a diagnostic circuit. The amplifier is capable of being coupled to an external oscillation source through an input pad and an output pad to generate an oscillating signal, the shaping circuit is capable of being coupled to the output pad, for shaping the oscillating signal to generate a clock signal, and the diagnostic circuit is capable of being coupled to the output pad, for asserting a ready signal when amplitude of the oscillating signal exceeds a predetermined portion of a full swing voltage.Type: GrantFiled: June 24, 2004Date of Patent: June 6, 2006Assignee: Faraday Technology Corp.Inventors: Jeng-Huang Wu, Sheng-Hua Chen
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Patent number: 7046493Abstract: An input/output buffer protection circuit, which comprises an I/O pad, an I/O buffer, an n-well control circuit, a gate control circuit, and a protection component. The I/O buffer includes a PMOS transistor and a NMOS transistor. The n-well control circuit is coupled to an n-well of the PMOS transistor. When an input voltage higher than a source voltage is applied, voltage at the n-well of the PMOS is increased by the n-well control circuit to the input voltage level. The gate control circuit is coupled to the gate terminal of the PMOS transistor and the input/output pad. When an input voltage higher than a source voltage is applied, voltage at the gate terminal of the PMOS is increased by the gate control circuit to the source voltage level. Wherein the gate control circuit comprises a transistor and the transistor transfers a high potential control voltage to the gate of the PMOS transistor in output mode.Type: GrantFiled: December 12, 2003Date of Patent: May 16, 2006Assignee: Faraday Technology Corp.Inventors: Sheng-Hua Chen, Hung-Yi Chang, Jeng-Huang Wu
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Publication number: 20050285689Abstract: A CMOS Pierce crystal oscillator. A clock generator with activation control, for generating a clock signal. The clock generator comprises an amplifier, a shaping circuit and a diagnostic circuit. The amplifier is capable of being coupled to an external oscillation source through an input pad and an output pad to generate an oscillating signal, the shaping circuit is capable of being coupled to the output pad, for shaping the oscillating signal to generate a clock signal, and the diagnostic circuit is capable of being coupled to the output pad, for asserting a ready signal when amplitude of the oscillating signal exceeds a predetermined portion of a full swing voltage.Type: ApplicationFiled: June 24, 2004Publication date: December 29, 2005Inventors: Jeng-Huang Wu, Sheng-Hua Chen
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Publication number: 20050128670Abstract: An input/output buffer protection circuit, which comprises an I/O pad, an I/O buffer, an n-well control circuit, a gate control circuit, and a protection component. The I/O buffer includes a PMOS transistor and a NMOS transistor. The n-well control circuit is coupled to an n-well of the PMOS transistor. When an input voltage higher than a source voltage is applied, voltage at the n-well of the PMOS is increased by the n-well control circuit to the input voltage level. The gate control circuit is coupled to the gate terminal of the PMOS transistor and the input/output pad. When an input voltage higher than a source voltage is applied, voltage at the gate terminal of the PMOS is increased by the gate control circuit to the source voltage level. Wherein the gate control circuit comprises a transistor and the transistor transfers a high potential control voltage to the gate of the PMOS transistor in output mode.Type: ApplicationFiled: December 12, 2003Publication date: June 16, 2005Inventors: Sheng-Hua Chen, Hung-Yi Chang, Jeng-Huang Wu
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Patent number: 6882188Abstract: An input/output buffer. An input/output circuit has a transmission terminal coupled to an I/O pad, and a floating N-well region. A P-gate control circuit conveys the second gate control signal to the gate of the first PMOS transistor. A feedback detection device is coupled between the transmission terminal and an N-well control circuit to output a feedback signal according to an input voltage at the I/O pad. The N-well control circuit adjusts the voltage level at the N-well region of the first PMOS transistor according to the feedback signal output from the feedback detection device.Type: GrantFiled: September 30, 2003Date of Patent: April 19, 2005Assignee: Faraday Technology Corp.Inventors: Sheng-Hua Chen, Hung-Yi Chang, Jeng-Huang Wu
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Publication number: 20050068069Abstract: An input/output buffer. An input/output circuit has a transmission terminal coupled to an I/O pad, and a floating N-well region. A P-gate control circuit conveys the second gate control signal to the gate of the first PMOS transistor. A feedback detection device is coupled between the transmission terminal and an N-well control circuit to output a feedback signal according to an input voltage at the I/O pad. The N-well control circuit adjusts the voltage level at the N-well region of the first PMOS transistor according to the feedback signal output from the feedback detection device.Type: ApplicationFiled: September 30, 2003Publication date: March 31, 2005Inventors: Sheng-Hua Chen, Hung-Yi Chang, Jeng-Huang Wu
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Patent number: 6861874Abstract: An input/output buffer. An input/output circuit is composed of a first PMOS transistor and a first NMOS transistor, has an I/O port coupled to an I/O pad, and a N-well region. An N-well control circuit controls the voltage level at the N-well region of the first PMOS transistor according to input signals at the I/O pad. A P-gate control circuit receives a second gate control signal and outputs to the gate of the first PMOS transistor. The P-gate control circuit is composed of a transmission gate and a third PMOS transistor. The transmission gate and the third PMOS transistor do not have to follow the design rule for ESD, and the wafer area required for the P-gate control circuit can be decreased because the P-gate control circuit is not directly connected to the I/O pad.Type: GrantFiled: October 7, 2003Date of Patent: March 1, 2005Assignee: Faraday Technology Corp.Inventors: Sheng-Hua Chen, Hung-Yi Chang, Jeng-Huang Wu