Patents by Inventor Sheng-Huang Huang

Sheng-Huang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220246838
    Abstract: The present disclosure relates to an integrated circuit. The integrated circuit includes a an inter-layer dielectric (ILD) structure laterally surrounding a conductive interconnect. A dielectric protection layer is disposed over the ILD structure and a passivation layer is disposed over the dielectric protection layer. The passivation layer includes a protrusion extending outward from an upper surface of the passivation layer. A bottom electrode continuously extends from over the passivation layer to between sidewalls of the passivation layer. A data storage element is over the bottom electrode and a top electrode is over the data storage element.
    Type: Application
    Filed: April 20, 2022
    Publication date: August 4, 2022
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Tong-Chern Ong, Wen-Ting Chu, Yu-Wen Liao, Kuei-Hung Shen, Kuo-Yuan Tu, Sheng-Huang Huang
  • Publication number: 20220246843
    Abstract: Some embodiments relate to a semiconductor structure having a magnetic tunnel junction (MTJ) on a substrate and a top electrode on the MTJ. A first segment of a top surface of the top electrode adjacent to a first sidewall of the top electrode is different from a second segment of the top surface of the top electrode adjacent to a second sidewall of the top electrode. A sidewall spacer comprises a first spacer on the first sidewall of the top electrode and a second spacer on the second sidewall of the top electrode. A first surface of the first spacer comprises a first curve and a second surface of the second spacer comprises a second curve. A dielectric layer is around the MTJ and top electrode.
    Type: Application
    Filed: April 21, 2022
    Publication date: August 4, 2022
    Inventors: Harry-Hak-Lay Chuang, Chen-Pin Hsu, Hung Cho Wang, Wen-Chun You, Sheng-Chang Chen, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang
  • Publication number: 20220216268
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory device. The method includes forming a first memory cell and a second memory cell over a substrate. A first dielectric layer is formed over and around the first and second memory cells. The first dielectric layer comprises sidewalls defining an opening spaced laterally between the first and second memory cells. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is disposed in the opening. A planarization process is performed on the first and second dielectric layers. At least a portion of the second dielectric layer is in the opening after the planarization process.
    Type: Application
    Filed: March 24, 2022
    Publication date: July 7, 2022
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Chang Chen, Sheng-Huang Huang
  • Patent number: 11380580
    Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming a memory device over a substrate and forming an etch stop layer over the memory device. An inter-level dielectric (ILD) layer is formed over the etch stop layer and laterally surrounding the memory device. One or more patterning process are performed to define a first trench extending from a top of the ILD layer to expose an upper surface of the etch stop layer. A removal process is performed to remove an exposed part of the etch stop layer. A conductive material is formed within the interconnect trench after performing the removal process.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: July 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Huang Huang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Chang Chen
  • Publication number: 20220157886
    Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing an etch stop layer over an interconnect layer having a conductive feature; depositing a protective layer over the etch stop layer; depositing a first dielectric layer over the protective layer; etching a via opening in the first dielectric layer, wherein the protective layer has a higher etch resistance to etching the via opening than that of the first dielectric layer; etching a portion of the protective layer exposed by the via opening; etching a portion of the etch stop layer exposed by the via opening, such that the via opening exposes the conductive feature; forming a bottom electrode via in the via opening; and forming a memory stack over the bottom electrode via.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 19, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Harry-Hak-Lay CHUANG, Sheng-Wen FU, Jun-Yao CHEN, Sheng-Huang HUANG, Hung-Cho WANG
  • Patent number: 11322543
    Abstract: Various embodiments of the present disclosure are directed towards a memory device including a protective sidewall spacer layer that laterally encloses a memory cell. An upper inter-level dielectric (ILD) layer overlying a substrate. The memory cell is disposed with the upper ILD layer. The memory cell includes a top electrode, a bottom electrode, and a magnetic tunnel junction (MTJ) structure disposed between the top and bottom electrodes. A sidewall spacer structure laterally surrounds the memory cell. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and the protective sidewall spacer layer. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different from the first material. A conductive wire overlying the first memory cell. The conductive wire contacts the top electrode and the protective sidewall spacer layer.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Chang Chen, Sheng-Huang Huang
  • Patent number: 11316096
    Abstract: The present disclosure relates to an integrated circuit. The integrated circuit includes a an inter-layer dielectric (ILD) structure laterally surrounding a conductive interconnect. A dielectric protection layer is disposed over the ILD structure and a passivation layer is disposed over the dielectric protection layer. The passivation layer includes a protrusion extending outward from an upper surface of the passivation layer. A bottom electrode continuously extends from over the passivation layer to between sidewalls of the passivation layer. A data storage element is over the bottom electrode and a top electrode is over the data storage element.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Tong-Chern Ong, Wen-Ting Chu, Yu-Wen Liao, Kuei-Hung Shen, Kuo-Yuan Tu, Sheng-Huang Huang
  • Publication number: 20220093684
    Abstract: Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes metal layers that are stacked over one another with dielectric layers disposed between. The metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ. A sidewall spacer surrounds an outer periphery of the top electrode. Less than an entirety of a top electrode surface is in direct electrical contact with a metal via connected to the upper metal layer.
    Type: Application
    Filed: November 23, 2021
    Publication date: March 24, 2022
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Jiunyu Tsai, Sheng-Huang Huang
  • Patent number: 11264561
    Abstract: A method of forming a magnetic random access memory (MRAM) device includes forming a bottom electrode layer over a substrate including an inter-metal dielectric (IMD) layer having a metal line therein; forming a barrier layer over the bottom electrode layer; forming a magnetic tunnel junction (MTJ) layer stack over the bottom electrode layer; forming a dielectric layer over the MTJ layer stack; forming an opening in the dielectric layer to expose the barrier layer; filling the opening in the dielectric layer with a top electrode; after filling the opening in the dielectric layer with the top electrode, etching the dielectric layer to expose the barrier layer; and patterning the MTJ layer stack to form an MTJ stack that exposes the bottom electrode layer.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Che Ku, Jun-Yao Chen, Sheng-Huang Huang, Jiun-Yu Tsai, Harry-Hak-Lay Chuang, Hung-Cho Wang
  • Publication number: 20220036932
    Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a first memory cell and a second memory cell over a substrate, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; depositing a first dielectric layer over the first and second memory cells, such that the first dielectric layer has a void between the first and second memory cells; depositing a second dielectric layer over the first dielectric layer; and forming a first conductive feature and a second conductive feature in the first and second dielectric layers and respectively connected with the top electrode of the first memory cell and the top electrode of the second memory cell.
    Type: Application
    Filed: July 30, 2020
    Publication date: February 3, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Harry-Hak-Lay CHUANG, Sheng-Huang HUANG, Hung-Cho WANG, Sheng-Chang CHEN
  • Publication number: 20220029093
    Abstract: A method for fabricating the semiconductor device is provided. The method includes depositing a first dielectric layer; forming a first memory cell over the first dielectric layer; depositing a second dielectric layer over the first memory cell; and forming a second memory cell over the second dielectric layer. Forming the first memory cell includes depositing a first resistance switching layer over the first dielectric layer and performing a first physical etching process to pattern the first resistance switching layer into a first resistance switching element. Forming the second memory cell includes depositing a second resistance switching layer over the second dielectric layer and performing a chemical etching process to pattern the second resistance switching layer into a second resistance switching element.
    Type: Application
    Filed: July 21, 2020
    Publication date: January 27, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Harry-Hak-Lay CHUANG, Sheng-Huang HUANG, Hung-Cho WANG
  • Publication number: 20220020920
    Abstract: A memory device includes a bottom electrode, a magnetic tunnel junction (MTJ) stack, a top electrode, and a sidewall spacer. The MTJ stack is over the bottom electrode. The top electrode is over the MTJ stack. The sidewall spacer laterally surrounds the MTJ stack and the top electrode. The sidewall spacer has an outermost sidewall laterally set back from an outermost sidewall of the bottom electrode.
    Type: Application
    Filed: March 24, 2021
    Publication date: January 20, 2022
    Inventors: Jun-Yao CHEN, Sheng-Huang HUANG, Hung-Cho WANG, Harry-Hak-Lay CHUANG
  • Patent number: 11217627
    Abstract: A method of forming a MRAM device includes forming an interconnect structure spanning a memory region and a peripheral region; forming a MTJ stack over the interconnect structure within the memory region; depositing a dielectric layer over the MTJ stack and spanning the memory region and the peripheral region; removing a first portion of the dielectric layer from the peripheral region, while leaving a second portion of the dielectric layer within the memory region; after removing the first portion of the dielectric layer from the peripheral region, forming a first IMD layer spanning the memory region and the peripheral region; forming a dual damascene structure through the first IMD layer to a metallization pattern of the interconnect structure within the peripheral region; and after forming the dual damascene structure within the peripheral region, forming a top electrode via in contact with a top electrode of the MTJ stack.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Harry-Hak-Lay Chuang, Jiun-Yu Tsai, Sheng-Huang Huang, Ming-Che Ku, Hung-Cho Wang
  • Publication number: 20210384413
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a memory cell stack over a substrate. The memory cell stack includes a top electrode. A sidewall spacer structure is formed around the memory cell stack. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. A dielectric structure is formed over the sidewall spacer structure. A first etch process is performed on the dielectric structure and the second sidewall spacer layer to define an opening above the top electrode. The second sidewall spacer layer and the dielectric structure are etched at a higher rate than the protective sidewall spacer layer during the first etch process. A top electrode via is formed within the opening.
    Type: Application
    Filed: August 19, 2021
    Publication date: December 9, 2021
    Inventors: Yao-Wen Chang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsung-Hsueh Yang, Yuan-Tai Tseng, Sheng-Huang Huang, Chia-Hua Lin
  • Publication number: 20210375987
    Abstract: Various embodiments of the present disclosure are directed towards a memory device including a protective sidewall spacer layer that laterally encloses a memory cell. An upper inter-level dielectric (ILD) layer overlying a substrate. The memory cell is disposed with the upper ILD layer. The memory cell includes a top electrode, a bottom electrode, and a magnetic tunnel junction (MTJ) structure disposed between the top and bottom electrodes. A sidewall spacer structure laterally surrounds the memory cell. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and the protective sidewall spacer layer. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different from the first material. A conductive wire overlying the first memory cell. The conductive wire contacts the top electrode and the protective sidewall spacer layer.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 2, 2021
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Chang Chen, Sheng-Huang Huang
  • Patent number: 11189659
    Abstract: Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes metal layers that are stacked over one another with dielectric layers disposed between. The metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ. A sidewall spacer surrounds an outer periphery of the top electrode. Less than an entirety of a top electrode surface is in direct electrical contact with a metal via connected to the upper metal layer.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Jiunyu Tsai, Sheng-Huang Huang
  • Publication number: 20210351345
    Abstract: Some embodiments relate to an integrated chip having a memory cell overlying a substrate and comprising a top electrode. A top electrode via overlies the top electrode. A width of an upper surface of the top electrode via is greater than a width of an upper surface of the top electrode. A conductive via overlies the top electrode via. A width of an upper surface of the conductive via is greater than the width of the upper surface of the top electrode via.
    Type: Application
    Filed: July 21, 2021
    Publication date: November 11, 2021
    Inventors: Harry-Hak-Lay Chuang, Chen-Pin Hsu, Hung Cho Wang, Wen-Chun You, Sheng-Chang Chen, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang
  • Publication number: 20210313394
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an Nth metal layer in a memory region and a periphery region, the periphery region spanning a wider area than the memory region, a plurality of magnetic tunneling junctions (MTJs) over the Nth metal layer, the plurality of MTJs having at least one of mixed pitches and mixed sizes, a top electrode via over each of the plurality of MTJs, and an (N+M)th metal layer over the plurality of MTJs. A method for manufacturing the semiconductor structure is also disclosed.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Inventors: ALEXANDER KALNITSKY, SHENG-HUANG HUANG, HARRY-HAK-LAY CHUANG, JIUNYU TSAI, HUNG CHO WANG
  • Patent number: 11121308
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a magnetoresistive random access memory (MRAM) cell over a substrate. A dielectric structure overlies the substrate. The MRAM cell is disposed within the dielectric structure. The MRAM cell includes a magnetic tunnel junction (MTJ) sandwiched between a bottom electrode and a top electrode. A conductive wire overlies the top electrode. A sidewall spacer structure continuously extends along a sidewall of the MTJ and the top electrode. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different than the first material.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Chang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsung-Hsueh Yang, Yuan-Tai Tseng, Sheng-Huang Huang, Chia-Hua Lin
  • Publication number: 20210273156
    Abstract: The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation the same. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. Two protection layers sequentially surround a sidewall of the MTJ. The two protection layers have etch selectivity over one another.
    Type: Application
    Filed: December 11, 2020
    Publication date: September 2, 2021
    Inventors: Sheng-Chang CHEN, Harry-Hak-Lay CHUANG, Hung Cho WANG, Sheng-Huang HUANG