Patents by Inventor Sheng-Huang Huang
Sheng-Huang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240147734Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a memory cell overlying a substrate and comprising a top electrode. A sidewall spacer structure is disposed along sidewalls of the memory cell. The sidewall spacer structure comprises a first spacer layer on the memory cell, a second spacer layer around the first spacer layer, and a third spacer layer around the second spacer layer. The second spacer layer comprises a lateral segment adjacent to a vertical segment. The lateral segment abuts the top electrode and has a top surface aligned with or disposed below a top surface of the top electrode. A first conductive structure overlies the memory cell and contacts the lateral segment and the top electrode.Type: ApplicationFiled: January 10, 2024Publication date: May 2, 2024Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Chang Chen, Sheng-Huang Huang
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Publication number: 20240090340Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device surrounded by a dielectric structure disposed over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A bottom electrode via couples the bottom electrode to a lower interconnect. A top electrode via couples the top electrode to an upper interconnect. A bottommost surface of the top electrode via is directly over the top electrode and has a first width that is smaller than a second width of a bottommost surface of the bottom electrode via.Type: ApplicationFiled: November 16, 2023Publication date: March 14, 2024Inventors: Ming-Che Ku, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang
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Patent number: 11910619Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory device. The method includes forming a first memory cell and a second memory cell over a substrate. A first dielectric layer is formed over and around the first and second memory cells. The first dielectric layer comprises sidewalls defining an opening spaced laterally between the first and second memory cells. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is disposed in the opening. A planarization process is performed on the first and second dielectric layers. At least a portion of the second dielectric layer is in the opening after the planarization process.Type: GrantFiled: March 24, 2022Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Chang Chen, Sheng-Huang Huang
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Patent number: 11889769Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a magnetic tunnel junction arranged between a bottom electrode and a top electrode and surrounded by a dielectric structure disposed over a substrate. The top electrode has a width that decreases as a height of the top electrode increases. A bottom electrode via couples the bottom electrode to a lower interconnect. An upper interconnect structure is coupled to the top electrode. The upper interconnect structure has a vertically extending surface that is disposed laterally between first and second outermost sidewalls of the upper interconnect structure and along a sidewall of the top electrode. The vertically extending surface and the first outermost sidewall are connected to a bottom surface of the upper interconnect structure that is vertically below a top of the top electrode.Type: GrantFiled: July 25, 2022Date of Patent: January 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Che Ku, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang
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Publication number: 20230389443Abstract: A memory device includes a bottom electrode, a magnetic tunnel junction (MTJ) stack, a top electrode, and a sidewall spacer. The MTJ stack is over the bottom electrode. The top electrode is over the MTJ stack. The sidewall spacer laterally surrounds the MTJ stack and the top electrode. The sidewall spacer has an outermost sidewall laterally set back from an outermost sidewall of the bottom electrode.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Jun-Yao CHEN, Sheng-Huang HUANG, Hung-Cho WANG, Harry-Hak-Lay CHUANG
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Publication number: 20230389445Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a memory cell stack over a substrate. The memory cell stack includes a top electrode. A sidewall spacer structure is formed around the memory cell stack. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. A dielectric structure is formed over the sidewall spacer structure. A first etch process is performed on the dielectric structure and the second sidewall spacer layer to define an opening above the top electrode. The second sidewall spacer layer and the dielectric structure are etched at a higher rate than the protective sidewall spacer layer during the first etch process. A top electrode via is formed within the opening.Type: ApplicationFiled: August 3, 2023Publication date: November 30, 2023Inventors: Yao-Wen Chang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsung-Hsueh Yang, Yuan-Tai Tseng, Sheng-Huang Huang, Chia-Hua Lin
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Publication number: 20230389446Abstract: The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation the same. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. Two protection layers sequentially surround a sidewall of the MTJ. The two protection layers have etch selectivity over one another.Type: ApplicationFiled: August 8, 2023Publication date: November 30, 2023Inventors: Sheng-Chang CHEN, Harry-Hak-Lay CHUANG, Hung Cho WANG, Sheng-Huang HUANG
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Patent number: 11832529Abstract: The present disclosure relates to an integrated circuit. The integrated circuit includes a an inter-layer dielectric (ILD) structure laterally surrounding a conductive interconnect. A dielectric protection layer is disposed over the ILD structure and a passivation layer is disposed over the dielectric protection layer. The passivation layer includes a protrusion extending outward from an upper surface of the passivation layer. A bottom electrode continuously extends from over the passivation layer to between sidewalls of the passivation layer. A data storage element is over the bottom electrode and a top electrode is over the data storage element.Type: GrantFiled: April 20, 2022Date of Patent: November 28, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Tong-Chern Ong, Wen-Ting Chu, Yu-Wen Liao, Kuei-Hung Shen, Kuo-Yuan Tu, Sheng-Huang Huang
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Publication number: 20230371275Abstract: A semiconductor device according to the present disclosure includes a first conductive feature and a second conductive feature in a first dielectric layer, a buffer layer over the first dielectric layer, a second dielectric layer over the buffer layer, a first bottom via extending through the buffer layer and the second dielectric layer, a second bottom via extending through the buffer layer and the second dielectric layer, a first bottom electrode disposed on the first bottom via, a second bottom electrode disposed on the second bottom via, a first magnetic tunnel junction (MTJ) stack over the first bottom electrode, and a second MTJ stack over the second bottom electrode. The first MTJ stack and the second MTJ stack have a same thickness. The first MTJ stack has a first width and the second MTJ stack has a second width greater than the first width.Type: ApplicationFiled: August 3, 2022Publication date: November 16, 2023Inventors: Yu-Jen Wang, Sheng-Huang Huang, Harry-Hak-Lay Chuang, Hung Cho Wang, Ching-Huang Wang, Kuo-Feng Huang
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Publication number: 20230371396Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate. The bottom electrode has a first thickness along an outermost edge and a second thickness between the outermost edge and a lateral center of the bottom electrode. The first thickness is larger than the second thickness. A data storage structure is over the bottom electrode and a top electrode is over the data storage structure.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Tong-Chern Ong, Wen-Ting Chu, Yu-Wen Liao, Kuei-Hung Shen, Kuo-Yuan Tu, Sheng-Huang Huang
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Patent number: 11818962Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a memory cell stack over a substrate. The memory cell stack includes a top electrode. A sidewall spacer structure is formed around the memory cell stack. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. A dielectric structure is formed over the sidewall spacer structure. A first etch process is performed on the dielectric structure and the second sidewall spacer layer to define an opening above the top electrode. The second sidewall spacer layer and the dielectric structure are etched at a higher rate than the protective sidewall spacer layer during the first etch process. A top electrode via is formed within the opening.Type: GrantFiled: August 19, 2021Date of Patent: November 14, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yao-Wen Chang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsung-Hsueh Yang, Yuan-Tai Tseng, Sheng-Huang Huang, Chia-Hua Lin
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Publication number: 20230345842Abstract: A memory device includes a memory unit and a shielding element disposed on the memory unit. The memory unit includes a bottom electrode, a memory element disposed on the bottom electrode, and a top electrode disposed on the memory element. The shielding element is disposed on the memory unit to deviate an external magnetic field away from the memory element.Type: ApplicationFiled: April 22, 2022Publication date: October 26, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Cho WANG, Sheng-Huang HUANG, Yuan-Jen LEE, Jiunyu TSAI, Keng-Ming KUO, Jun-Yao CHEN, Harry-Hak-Lay CHUANG
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Publication number: 20230345739Abstract: The present disclosure provides a semiconductor structure, including a memory region, a logic region adjacent to the memory region, a first magnetic tunneling junction (MTJ) cell and a second MTJ cell over the memory region, and a carbon-based layer over the memory region, wherein the carbon-based layer includes a recess between the first MTJ cell and the second MTJ cell.Type: ApplicationFiled: June 21, 2023Publication date: October 26, 2023Inventors: HARRY-HAK-LAY CHUANG, SHENG-HUANG HUANG, KENG-MING KUO, HUNG CHO WANG
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Patent number: 11723219Abstract: The present disclosure provides a semiconductor structure, including a memory region, a logic region adjacent to the memory region, a first magnetic tunneling junction (MTJ) cell and a second MTJ cell over the memory region, and a carbon-based layer over the memory region, wherein the carbon-based layer includes a recess between the first MTJ cell and the second MTJ cell.Type: GrantFiled: April 29, 2021Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Harry-Hak-Lay Chuang, Sheng-Huang Huang, Keng-Ming Kuo, Hung Cho Wang
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Publication number: 20230189657Abstract: Improved methods of patterning magnetic tunnel junctions (MTJs) for magnetoresistive random-access memory (MRAM) and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes depositing a bottom electrode layer over a semiconductor substrate; depositing an MTJ film stack over the bottom electrode layer; depositing a top electrode layer over the MTJ film stack; patterning the top electrode layer; performing a first etch process to pattern the MTJ film stack; performing a first trim process on the MTJ film stack; after performing the first trim process, depositing a first spacer layer over the MTJ film stack; and after depositing the first spacer layer, performing a second etch process to pattern the first spacer layer, the MTJ film stack, and the bottom electrode layer to form an MRAM cell.Type: ApplicationFiled: April 20, 2022Publication date: June 15, 2023Inventors: Harry-HakLay Chuang, Hung Cho Wang, Sheng-Huang Huang, Hung-Yu Chang, Keng-Ming Kuo
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Patent number: 11678493Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an Nth metal layer in a memory region and a periphery region, the periphery region spanning a wider area than the memory region, a plurality of magnetic tunneling junctions (MTJs) over the Nth metal layer, the plurality of MTJs having at least one of mixed pitches and mixed sizes, a top electrode via over each of the plurality of MTJs; and an (N+M)th metal layer over the plurality of MTJs. A method for manufacturing the semiconductor structure is also disclosed.Type: GrantFiled: June 21, 2021Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Alexander Kalnitsky, Sheng-Huang Huang, Harry-Hak-Lay Chuang, Jiunyu Tsai, Hung Cho Wang
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Publication number: 20230140896Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a first memory cell and a second memory cell over a substrate, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; depositing a first dielectric layer over the first and second memory cells, such that the first dielectric layer has a void between the first and second memory cells; depositing a second dielectric layer over the first dielectric layer; and forming a first conductive feature and a second conductive feature in the first and second dielectric layers and respectively connected with the top electrode of the first memory cell and the top electrode of the second memory cell.Type: ApplicationFiled: January 9, 2023Publication date: May 11, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Harry-Hak-Lay CHUANG, Sheng-Huang HUANG, Hung-Cho WANG, Sheng-Chang CHEN
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Patent number: 11646167Abstract: A keyboard device includes plural key structures. Each key structure includes a base plate, a keycap, a membrane circuit board, a connecting member and an elastic element. The keycap includes a pressing post. The membrane circuit board is arranged between the base plate and the keycap. The connecting member is penetrated through the membrane circuit board and connected between the keycap and the base plate. The keycap is movable upwardly or downwardly relative to the membrane circuit board. The elastic element is arranged between the keycap and the membrane circuit board. The elastic element includes a resilience piece and plural supporting ribs. The plural supporting ribs are arranged between the resilience piece and the keycap. The plural supporting ribs are contacted with the pressing post of the keycap. Consequently, there is a gap between the pressing post and the resilience piece.Type: GrantFiled: April 1, 2022Date of Patent: May 9, 2023Assignee: PRIMAX ELECTRONICS LTD.Inventors: Chuang-Shu Jhuang, Dan Li, Sheng-Huang Huang
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Publication number: 20230061985Abstract: A MRAM device includes a substrate, a first bottom electrode, a first MTJ stack, a first spacer, a topography-smoothing layer and a second ILD layer. The substrate includes a first ILD layer having a metal line. The first MTJ stack is over the first bottom electrode. The first spacer surrounds sidewalls of the first MTJ stack. The topography-smoothing layer extends over a top surface of the first ILD layer, along sidewalls of the first bottom electrode the first spacer. The topography-smoothing layer has a top portion over the first MTJ stack and a first side portion laterally surrounding the first spacer. The first side portion has a maximal lateral thickness greater than a maximal vertical thickness of the top portion. The second ILD layer is over the topography-smoothing layer and has a material different from a material of the topography-smoothing layer.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Harry-Hak-Lay CHUANG, Sheng-Chang CHEN, Hung Cho WANG, Sheng-Huang HUANG
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Publication number: 20230065850Abstract: An integrated circuit device includes a substrate, a memory cell, a magnetic shielding element, an interlayer dielectric layer, and a metallization pattern. The memory cell is over the substrate. The memory cell includes a bottom electrode, a resistance switching element over the bottom electrode, a top electrode over the resistance switching element. The magnetic shielding element is around the memory cell. The interlayer dielectric layer surrounds the memory cell and the magnetic shielding element. The metallization pattern is in the interlayer dielectric layer and connected to the top electrode.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yuan-Jen LEE, Harry-Hak-Lay CHUANG, Tien-Wei CHIANG, Hung Cho WANG, Kuei-Hung SHEN, Sheng-Huang HUANG