Patents by Inventor Sheng Liang

Sheng Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11759931
    Abstract: A nail drive device of electric nail gun includes a nailing rod and a rotary actuator that can output a specific rotation angle and can drive the nailing rod to move downward for nailing. Specifically, the rotary actuator includes a stator and a rotor surrounding it, between the stator and the rotor, even groups of electro-magnetic mutual action components are configured in pairs, to generate a tangential force to drive the rotor to rotate for a specific rotation angle, and to drive the nailing rod to move for a nailing stroke. The nailing stroke can be determined by the specific rotation angle. Thus, through the above configuration of the rotary actuator, the structure of the electric nail gun can be simplified.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: September 19, 2023
    Assignee: DE POAN PNEUMATIC CORP.
    Inventors: I-Tsung Wu, Chia-Sheng Liang, Zhen-Liang Liao, Wen-Chin Chen
  • Patent number: 11756962
    Abstract: Provided is a semiconductor device including a substrate, one hybrid fin, a gate, and a dielectric structure. The substrate includes at least two fins. The hybrid fin is disposed between the at least two fins. The gate covers portions of the at least two fins and the hybrid fin. The dielectric structure lands on the hybrid fin to divide the gate into two segment. The two segments are electrically isolated to each other by the dielectric structure and the hybrid fin. The hybrid fin includes a first portion, disposed between the two segments of the gate; and a second portion, disposed aside the first portion, wherein a top surface of the second portion is lower than a top surface of the first portion.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-San Chien, Chun-Sheng Liang, Jhon-Jhy Liaw, Kuo-Hua Pan, Hsin-Che Chiang
  • Publication number: 20230282484
    Abstract: A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.
    Type: Application
    Filed: May 12, 2023
    Publication date: September 7, 2023
    Inventors: Shao-Jyun Wu, Sheng-Liang Pan, Huan-Just Lin
  • Publication number: 20230272795
    Abstract: Disclosed are a scroll compressor and a method for assembling a non-orbiting scroll of the scroll compressor. The scroll compressor includes: a scroll mechanism including a non-orbiting scroll which includes a non-orbiting scroll end plate and a non-orbiting scroll wrap and an outer peripheral wall; and a main bearing seat for supporting the scroll mechanism including a main body part and an axial seat portion whose inner peripheral surface is formed with a circumferential annular groove. The scroll compressor further includes an elastic ring provided between the outer peripheral wall and the axial seat portion and a push structure for forcing the elastic ring to expand radially outward, so that a part of the elastic ring in a radial direction is inserted into the circumferential annular groove to limit axial movement of the non-orbiting scroll away from the main bearing seat.
    Type: Application
    Filed: October 27, 2020
    Publication date: August 31, 2023
    Applicant: Emerson Climate Technologies (Suzhou) Co., Ltd.
    Inventors: Erfeng YANG, Sheng LIANG, Zhenfei DUAN
  • Publication number: 20230268223
    Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a gate electrode, a gate electrode contact layer over the gate electrode, forming a dielectric layer over the gate electrode contact layer, and performing an etch through the dielectric layer, the etch forming an opening that exposes the gate electrode contact layer. The method further includes performing a post-etch treatment on the opening formed by the etch process by exposing the opening to a plasma. The method further includes forming gate electrode contacts in the openings after the post-etch treatment by a bottom-up deposition process.
    Type: Application
    Filed: February 24, 2022
    Publication date: August 24, 2023
    Inventors: Po-Chuan Wang, Guan-Xuan Chen, Chia-Yang Hung, Sheng-Liang Pan, Huan-Just Lin
  • Publication number: 20230268404
    Abstract: A method of applying and then removing a protective layer over a portion of a gate stack is provided. The protective layer is deposited and then a plasma precursor is separated into components. Neutral radicals are then utilized in order to remove the protective layer. In some embodiments the removal also forms a protective by-product which helps to protect underlying layers from damage during the etching process.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 24, 2023
    Inventors: Ming-Chia Tai, Ju-Yuan Tzeng, Hsin-Che Chiang, Yuan-Sheng Huang, Chun-Sheng Liang
  • Publication number: 20230268406
    Abstract: A method includes forming a semiconductor fin over a substrate; forming a gate structure over the semiconductor fin, the gate structure comprising: a first metallic layer; a second metallic layer over the first metallic layer, wherein the first metallic layer is a metal compound of a first element and a second element and the second metallic layer is a single-element metal of the second element; and an oxide layer between the first metallic layer and the second metallic layer.
    Type: Application
    Filed: April 24, 2023
    Publication date: August 24, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che CHIANG, Ju-Yuan TZENG, Chun-Sheng LIANG, Chih-Yang YEH, Shu-Hui WANG, Jeng-Ya David YEH
  • Patent number: 11735662
    Abstract: A method of semiconductor fabrication includes forming a dielectric layer over a substrate. A dummy gate structure is formed on the dielectric layer, which defines a dummy gate dielectric region. A portion of the dielectric layer not included in the dummy gate dielectric region is etched to form a dielectric etch back region. A spacer element is formed on a portion of the dielectric etch back region, which abuts the dummy gate structure, and defines a spacer dielectric region A height of the dummy gate dielectric region is greater than the height of the spacer dielectric region. A recessed portion is formed in the substrate, over which a strained material is selectively grown to form a strained recessed region adjacent the spacer dielectric region. The dummy gate structure and the dummy gate dielectric region are removed. A gate electrode layer and a gate dielectric layer are formed.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Sheng Liang, Shih-Hsun Chang
  • Patent number: 11733798
    Abstract: A touch sensing system is provided. The touch sensing system includes a touch panel including touch sensors arranged in a grid along row and column directions; a touch controller including at least one transmission circuit to transmit a signal to the touch sensors and at least one reception circuit to detect a signal from the touch sensors; and a switching circuit to selectively connect each of the touch sensors to the at least one transmission circuit and the at least one reception circuit in accordance with an operation mode. The switching circuit connects each of the touch sensors to the at least one reception circuit in a touch mode and connects a first portion of the touch sensors to the at least one reception circuit and a second portion of the touch sensors to the at least one transmission circuit in a proximity mode.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: August 22, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Minsung Kim, Sanho Byun, Roots Huang, Yao Sheng Liang, Jungmoon Kim, Dongjo Park
  • Patent number: 11735481
    Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Jyun Wu, Hung-Chi Wu, Chia-Ching Lee, Pin-Hsuan Yeh, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Sheng-Liang Pan, Huan-Just Lin
  • Patent number: 11728232
    Abstract: A semiconductor package includes a package substrate having a top surface and a bottom surface, and a stiffener ring mounted on the top surface of the package substrate. The stiffener ring includes a reinforcement rib that is coplanar with the stiffener ring on the top surface of the package substrate. At least two compartments are defined by the stiffener ring and the reinforcement rib. At least two individual chip packages are mounted on chip mounting regions within the at least two compartments, respectively, thereby constituting a package array on the package substrate.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: August 15, 2023
    Assignee: MediaTek Inc.
    Inventors: Chi-Wen Pan, I-Hsuan Peng, Sheng-Liang Kuo, Yi-Jou Lin, Tai-Yu Chen
  • Publication number: 20230238302
    Abstract: A semiconductor package includes a substrate; a die mounted on a top surface of the substrate in a flip-chip fashion; and a lid mounted on the die and on a perimeter of the substrate. The lid includes a cover plate and four walls formed integral with the cover plate. A liquid-cooling channel is situated between the cover plate of the lid and a rear surface of the die for circulating a coolant relative to the semiconductor package.
    Type: Application
    Filed: March 30, 2023
    Publication date: July 27, 2023
    Applicant: MEDIATEK INC.
    Inventors: Chia-Hao Hsu, Tai-Yu Chen, Sheng-Liang Kuo, Bo-Jiun Yang
  • Publication number: 20230214141
    Abstract: A computer device, a setting method for a memory module, and a mainboard are provided. The computer device includes a memory module, a processor, and the mainboard. A basic input output system (BIOS) of the mainboard stores a custom extreme memory profile (XMP). When the processor executes the BIOS, so that the computer device displays a user interface (UI), the BIOS displays multiple default XMPs stored in the memory module and the custom XMP through the UI. The BIOS stores one of the default XMPs and the custom XMP to the memory module according to a selecting result of the one of the default XMPs and the custom XMP displayed on the UI.
    Type: Application
    Filed: March 16, 2022
    Publication date: July 6, 2023
    Applicant: GIGA-BYTE TECHNOLOGY CO.,LTD.
    Inventors: Chia-Chih Chien, Sheng-Liang Kao, Chen-Shun Chen, Chieh-Fu Chung, Hua-Yi Wu
  • Publication number: 20230215475
    Abstract: A computer device, a setting method for a memory module, and a mainboard are provided. The computer device includes a memory module, a processor, and the mainboard. A basic input output system (BIOS) of the mainboard stores an extreme memory profile (XMP). When the processor performs the BIOS so that the computer device displays a user interface (UI), the BIOS displays an overclocking option corresponding to the XMP in a selection list of the UI. When the BIOS receives a selection request corresponding to the overclocking option of the selection list, the BIOS reads multiple memory setting parameters corresponding to the XMP, and configures the memory module according to the memory setting parameters.
    Type: Application
    Filed: March 22, 2022
    Publication date: July 6, 2023
    Applicant: GIGA-BYTE TECHNOLOGY CO.,LTD.
    Inventors: Chia-Chih Chien, Sheng-Liang Kao, Chen-Shun Chen
  • Publication number: 20230201843
    Abstract: A centrifuge device includes a main body, a driving module, a centrifuge assembly, and a pipe. The main body has an accommodating space and a slot. The slot is connected to the accommodating space. The driving module is at least partially disposed in the accommodating space. The centrifuge assembly is disposed on the main body. A part of the centrifuge assembly is located in the accommodating space and connected to the driving module. The driving module is adapted to drive the centrifuge assembly to rotate. The pipe is connected to the part of the centrifuge assembly and extends out of the main body through the slot.
    Type: Application
    Filed: May 11, 2022
    Publication date: June 29, 2023
    Applicant: Sangtech Lab Inc.
    Inventor: Cheng-Sheng Liang
  • Patent number: 11688606
    Abstract: A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Jyun Wu, Sheng-Liang Pan, Huan-Just Lin
  • Patent number: 11680568
    Abstract: A compressor includes a compression mechanism and a driveshaft that drives the compression mechanism. The driveshaft may include a first axially extending passage, a second axially extending passage, and a lubricant distribution passage. The first and second axially extending passages may be radially offset from each other and may intersect each other at an overlap region. The first and second axially extending passages are in fluid communication with each other at the overlap region. The lubricant distribution passage may extend from the first axially extending passage through an outer diametrical surface of the driveshaft. The lubricant distribution passage may be disposed at a first axial distance from a first axial end of the driveshaft. A first axial end of the overlap region may be disposed at a second axial distance from the first axial end of the driveshaft. The first axial distance may be greater than the second axial distance.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 20, 2023
    Assignee: Emerson Climate Technologies, Inc.
    Inventors: Jesus Angel Nohales Herraiz, Xiaogeng Su, Sheng Liang
  • Publication number: 20230182276
    Abstract: A nail drive method applied in an electric nail gun, in which a rotary actuator is driven to generate forward rotational kinetic energy for nailing. The rotary actuator has paired wire bundles and magnetic lines arranged in circumferential directions. The nail drive method comprises boosting a pre-loaded voltage of a battery to generate a peak voltage, and storing the electric charge generated by the peak voltage, and then releasing the peak voltage and its electric charge to the rotary actuator through a nailing signal, so that the wire bundles can generate a current to interact with the magnetic lines to generate a tangential force, so that the magnetic lines can drive the rotor to rotate for a specific angle, and the rotary actuator can directly generate a forward rotational kinetic energy for nailing. Thus, the energy conversion structure installed in the conventional electric nail gun can be omitted.
    Type: Application
    Filed: November 2, 2022
    Publication date: June 15, 2023
    Inventors: I-Tsung Wu, Chia-Sheng Liang, Zhen-Liang Liao, Wen-Chin Chen
  • Publication number: 20230178361
    Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a first opening through a dielectric layer, the opening exposing a conductive region. A wet cleaning is used after the forming the first opening, and the first opening is treated after the wet cleaning the first opening, the treating the first opening comprising turning a sidewall treatment precursor and a bottom treatment precursor into a first plasma mixture, the sidewall treatment precursor being different from the bottom treatment precursor. The first opening is filled with a conductive material after the treating the first opening.
    Type: Application
    Filed: April 13, 2022
    Publication date: June 8, 2023
    Inventors: Chia-Yang Hung, Huan-Just Lin, Sheng-Liang Pan, Yungtzu Chen, Po-Chuan Wang, Guan-Xuan Chen
  • Patent number: 11670697
    Abstract: A semiconductor device includes a substrate comprising a semiconductor fin, a gate structure over the semiconductor fin, and source/drain structures over the semiconductor fin and on opposite sides of the gate structure. The gate stack comprises a high-k dielectric layer; a first work function metal layer over the high-k dielectric layer; an oxide of the first work function metal layer over the first work function metal layer; and a second work function metal layer over the oxide of the first work function metal layer, in which the first and second work function metal layers have different compositions; and a gate electrode over the second work function metal layer.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Chih-Yang Yeh, Shu-Hui Wang, Jeng-Ya David Yeh