Patents by Inventor Sheng-Ming Wang

Sheng-Ming Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240387163
    Abstract: A method for drying a wafer includes a cleaning step, a liquid replacing step, and a drying step. In the cleaning step, a workpiece located in a process chamber is cleaned with a cleaning solution. In the liquid replacing step, a drying agent in gas phase is compressed to convert into liquid phase, and the drying agent in liquid phase is introduced to the process chamber to replace the cleaning solution. In the drying step, the cleaning solution is discharged out of the process chamber, and then the drying agent is converted from liquid phase back to gas phase and is discharged out of the process chamber.
    Type: Application
    Filed: July 7, 2023
    Publication date: November 21, 2024
    Inventors: TING-CHANG CHANG, CHUAN-WEI KUO, SHENG-YAO CHOU, SHIH-KAI LIN, HUNG-MING KUO, YU-BO WANG, PEI-JUN SUN
  • Publication number: 20240389334
    Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240389336
    Abstract: A semiconductor chip including a semiconductor substrate, an interconnect structure and memory devices is provided. The semiconductor substrate includes first transistors, and the first transistors are negative capacitance field effect transistors. The interconnect structure is disposed over the semiconductor substrate and electrically connected to the first transistors, and the interconnect structure includes stacked interlayer dielectric layers, interconnect wirings, and second transistors embedded in the stacked interlayer dielectric layers. The memory devices are embedded in the stacked interlayer dielectric layers and electrically connected to the second transistors.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Sheng-Chen Wang, Sai-Hooi Yeong, Yu-Ming Lin, Chao-I Wu
  • Patent number: 12148505
    Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240379408
    Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Lin-Yu Huang, Sheng-Tsung Wang, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20240360551
    Abstract: A semiconductor processing tool includes: a process chamber into which a semiconductor wafer is loaded; a support for securing the wafer loaded into the chamber tool; an inlet which introduces a first gas into the chamber for processing the wafer; and an exhaust system that exhausts gas from the chamber. The exhaust system includes: a first line coupled to the chamber to exhaust gas from the chamber; and a pump to draw gas through the first line from the chamber. The tool further includes a heating module having: a second line coupled to the first and a supply of a second gas, the second gas being flowed through the second line from the supply into the first line; and a heating element contained in the second line, the heating element heating the second gas in the second line before the second gas is flowed into the first line.
    Type: Application
    Filed: April 28, 2023
    Publication date: October 31, 2024
    Inventors: Sheng-chun Yang, Yi-Ming Lin, Chun Chang, Che Kang Liu, Kaijun Jan, Xuan-Yang Zheng, Tzu-Chuan Chao, Weigang Wu, Chih-Yuan Wang, Ren-Jyue Wang
  • Patent number: 12131942
    Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lin-Yu Huang, Sheng-Tsung Wang, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20240357828
    Abstract: A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and channel layers. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure.
    Type: Application
    Filed: June 30, 2024
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chen Wang, Meng-Han Lin, Sai-Hooi Yeong, Yu-Ming Lin, Han-Jong Chia
  • Publication number: 20240357834
    Abstract: A gated ferroelectric memory cell includes a dielectric material layer disposed over a substrate, a metallic bottom electrode, a ferroelectric dielectric layer contacting a top surface of the bottom electrode, a pillar semiconductor channel overlying the ferroelectric dielectric layer and capacitively coupled to the metallic bottom electrode through the ferroelectric dielectric layer, a gate dielectric layer including a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the pillar semiconductor channel, a gate electrode strip overlying the horizontal gate dielectric portion and laterally surrounding the tubular gate dielectric portion and a metallic top electrode contacting a top surface of the pillar semiconductor channel.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Inventors: Bo-Feng Young, Yu-Ming Lin, Han-Jong Chia, Sheng-Chen Wang, Sai-Hooi Yeong
  • Publication number: 20240347463
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a fin disposed over a substrate, a gate structure disposed over a channel region of the fin, such that the gate structure traverses source/drain regions of the fin, a device-level interlayer dielectric (ILD) layer of a multi-layer interconnect structure disposed over the substrate, wherein the device-level ILD layer includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer disposed over the second dielectric layer, wherein a material of the third dielectric layer is different than a material of the second dielectric layer and a material of the first dielectric layer. The semiconductor device further comprises a gate contact to the gate structure disposed in the device-level ILD layer and a source/drain contact to the source/drain regions disposed in the device-level ILD layer.
    Type: Application
    Filed: June 25, 2024
    Publication date: October 17, 2024
    Inventors: Lin-Yu Huang, Sheng-Tsung Wang, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20240331754
    Abstract: 3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.
    Type: Application
    Filed: June 13, 2024
    Publication date: October 3, 2024
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chao-I Wu, Sheng-Chen Wang, Yu-Ming Lin
  • Publication number: 20240321637
    Abstract: The present disclosure provides a semiconductor structure. The structure includes a semiconductor substrate, a gate stack over a first portion of a top surface of the semiconductor substrate; and a laminated dielectric layer over at least a portion of a top surface of the gate stack. The laminated dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is formed of a material having a dielectric constant lower than a dielectric constant of a material used to form the second sublayer and the material used to form the second sublayer has an etch selectivity higher than an etch selectivity of the material used to form the first sublayer.
    Type: Application
    Filed: May 1, 2024
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Lin Chuang, Chia-Hao Chang, Sheng-Tsung Wang, Lin-Yu Huang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20240290672
    Abstract: A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.
    Type: Application
    Filed: May 6, 2024
    Publication date: August 29, 2024
    Inventors: Sheng-Chieh Chen, Wei-Ming Wang, Ming-Lun Lee, Chih-Ren Hsieh, Ming Chyi Liu
  • Publication number: 20240290661
    Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.
    Type: Application
    Filed: May 6, 2024
    Publication date: August 29, 2024
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Sheng-Tsung Wang, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 12069868
    Abstract: A gated ferroelectric memory cell includes a dielectric material layer disposed over a substrate, a metallic bottom electrode, a ferroelectric dielectric layer contacting a top surface of the bottom electrode, a pillar semiconductor channel overlying the ferroelectric dielectric layer and capacitively coupled to the metallic bottom electrode through the ferroelectric dielectric layer, a gate dielectric layer including a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the pillar semiconductor channel, a gate electrode strip overlying the horizontal gate dielectric portion and laterally surrounding the tubular gate dielectric portion and a metallic top electrode contacting a top surface of the pillar semiconductor channel.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: August 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Han-Jong Chia, Sheng-Chen Wang, Yu-Ming Lin
  • Publication number: 20240276738
    Abstract: The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device has a substrate and a lower interconnect metal line disposed over the substrate. The memory device also has a selector channel disposed over the lower interconnect metal line and a selector gate electrode wrapping around a sidewall of the selector channel and separating from the selector channel by a selector gate dielectric. The memory device also has a memory cell disposed over and electrically connected to the selector channel and an upper interconnect metal line disposed over the memory cell. By placing the selector within the back-end interconnect structure, front-end space is saved, and more integration flexibility is provided.
    Type: Application
    Filed: April 24, 2024
    Publication date: August 15, 2024
    Inventors: Bo-Feng Young, Sheng-Chen Wang, Sai-Hooi Yeong, Yu-Ming Lin, Mauricio Manfrini, Han-Jong Chia
  • Publication number: 20240276726
    Abstract: A memory array device includes a stack of transistors over a semiconductor substrate, a first transistor of the stack being disposed over a second transistor of the stack. The first transistor includes a first memory film along a first word line and a first channel region along a source line and a bit line, the first memory film being disposed between the first channel region and the first word line. The second transistor includes a second memory film along a second word line and a second channel region along the source line and the bit line, the second memory film being disposed between the second channel region and the second word line. The memory array device includes a first via electrically connected to the first word line and a second via electrically connected to the second word line, the second staircase via and the first staircase via having different widths.
    Type: Application
    Filed: April 11, 2024
    Publication date: August 15, 2024
    Inventors: Meng-Han Lin, Feng-Cheng Yang, Sheng-Chen Wang, Sai-Hooi Yeong, Yu-Ming Lin, Han-Jong Chia
  • Patent number: 12063787
    Abstract: A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and channel layers. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: August 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Sheng-Chen Wang, Meng-Han Lin, Sai-Hooi Yeong, Yu-Ming Lin, Han-Jong Chia
  • Publication number: 20240268122
    Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.
    Type: Application
    Filed: April 17, 2024
    Publication date: August 8, 2024
    Inventors: Meng-Han Lin, Bo-Feng Young, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Sai-Hooi Yeong, Yu-Ming Lin
  • Patent number: 12055228
    Abstract: A valve for throttling gas flow from a semiconductor processing tool includes a valve body. A shaft extends through the valve body. The shaft defines an internal cavity and a first opening communicating with the internal cavity. A first deflector is positioned on the shaft proximate the first opening and directed at a first interface between the shaft and the valve body. A method for throttling gas flow from a semiconductor processing tool includes providing a gas in an internal cavity defined in a shaft of a valve and directing the gas through an opening defined in the shaft and communicating with the bore toward an interface between the shaft and a valve body of the valve supporting the shaft.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: August 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Chun Yang, Po-Chih Huang, Chang Chun, Xuan-Yang Zheng, Tzu-Chuan Chao, Ren-Jyue Wang, Yi-Ming Lin