Patents by Inventor Sheng-Ming Wang
Sheng-Ming Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250085764Abstract: A method of performing power saving control on a display device includes: generating, by a timing controller of the display device, a power saving start indication and a power saving end indication in response to changing of a refresh rate of the display device; receiving, by a source driver of the display device, the power saving start indication and the power saving end indication; in response to the power saving start indication, allowing a part of circuitry of the source driver to be powered down during a vertical blanking interval; and in response to the power saving end indication, allowing the powered down part of circuitry of the source driver to be woken up during the vertical blanking interval.Type: ApplicationFiled: September 7, 2023Publication date: March 13, 2025Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Hung-Yu Huang, Shu-Ming Chang, Chia-Hui Wang, Shiang-Wei Wang, Sheng-Wen Huang, Tsung-Yi Tsai
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Publication number: 20250089264Abstract: A 3D memory array has data storage structures provided at least in part by one or more vertical films that do not extend between vertically adjacent memory cells. The 3D memory array includes conductive strips and dielectric strips, alternately stacked over a substrate. The conductive strips may be laterally indented from the dielectric strips to form recesses. A data storage film may be disposed within these recesses. Any portion of the data storage film deposited outside the recesses may have been effectively removed, whereby the data storage film is essentially discontinuous from tier to tier within the 3D memory array. The data storage film within each tier may have upper and lower boundaries that are the same as those of a corresponding conductive strip. The data storage film may also be made discontinuous between horizontally adjacent memory cells.Type: ApplicationFiled: November 26, 2024Publication date: March 13, 2025Inventors: Sheng-Chen Wang, Feng-Cheng Yang, Meng-Han Lin, Sai-Hooi Yeong, Yu-Ming Lin, Han-Jong Chia
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Patent number: 12248353Abstract: A method of performing power saving control on a display device includes: generating, by a timing controller of the display device, a power saving start indication and a power saving end indication in response to changing of a refresh rate of the display device; receiving, by a source driver of the display device, the power saving start indication and the power saving end indication; in response to the power saving start indication, allowing a part of circuitry of the source driver to be powered down during a vertical blanking interval; and in response to the power saving end indication, allowing the powered down part of circuitry of the source driver to be woken up during the vertical blanking interval.Type: GrantFiled: September 7, 2023Date of Patent: March 11, 2025Assignee: HIMAX TECHNOLOGIES LIMITEDInventors: Hung-Yu Huang, Shu-Ming Chang, Chia-Hui Wang, Shiang-Wei Wang, Sheng-Wen Huang, Tsung-Yi Tsai
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Patent number: 12249640Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.Type: GrantFiled: November 30, 2023Date of Patent: March 11, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen
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Patent number: 12238926Abstract: In an embodiment, a device includes: a first dielectric layer having a first sidewall; a second dielectric layer having a second sidewall; a word line between the first dielectric layer and the second dielectric layer, the word line having an outer sidewall and an inner sidewall, the inner sidewall recessed from the outer sidewall, the first sidewall, and the second sidewall; a memory layer extending along the outer sidewall of the word line, the inner sidewall of the word line, the first sidewall of the first dielectric layer, and the second sidewall of the second dielectric layer; and a semiconductor layer extending along the memory layer.Type: GrantFiled: January 3, 2023Date of Patent: February 25, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Bo-Feng Young, Sai-Hooi Yeong, Han-Jong Chia, Sheng-Chen Wang, Yu-Ming Lin
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Publication number: 20240213168Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.Type: ApplicationFiled: February 6, 2024Publication date: June 27, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Sheng-Ming WANG, Tien-Szu CHEN, Wen-Chih SHEN, Hsing-Wen LEE, Hsiang-Ming FENG
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Publication number: 20240107250Abstract: A method for performing audio enhancement with aid of timing control includes: utilizing a UE to determine a first predetermined synchronization delay and notify a first earphone of the first predetermined synchronization delay, wherein a first DSP circuit in the first earphone is arranged to determine a synchronization point according to a first time point of a first event and the first predetermined synchronization delay for the first earphone; utilizing the UE to determine a second predetermined synchronization delay and notify a second earphone of the second predetermined synchronization delay, wherein a second DSP circuit in the second earphone is arranged to determine the synchronization point according to a second time point of a second event and the second predetermined synchronization delay for the second earphone; and utilizing the UE to receive first uplink audio data from the first earphone and receive second uplink audio data from the second earphone.Type: ApplicationFiled: December 6, 2022Publication date: March 28, 2024Applicant: MEDIATEK INC.Inventors: Hsi-Hsien Chen, Yili Wang, Chia-Wei Tao, Sheng-Ming Wang
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Patent number: 11894308Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.Type: GrantFiled: December 1, 2020Date of Patent: February 6, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Sheng-Ming Wang, Tien-Szu Chen, Wen-Chih Shen, Hsing-Wen Lee, Hsiang-Ming Feng
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Publication number: 20210091006Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.Type: ApplicationFiled: December 1, 2020Publication date: March 25, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Sheng-Ming WANG, Tien-Szu CHEN, Wen-Chih SHEN, Hsing-Wen LEE, Hsiang-Ming FENG
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Patent number: 10879159Abstract: A substrate, a semiconductor package thereof and a process of making the same are provided. The substrate comprises an upper circuit layer and a lower circuit layer, the upper circuit layer comprising at least one trace and at least one pad and the lower circuit layer comprising at least one trace and at least one pad, wherein the trace of the upper circuit layer and the trace of the lower circuit layer are not aligned.Type: GrantFiled: May 5, 2015Date of Patent: December 29, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tien-Szu Chen, Sheng-Ming Wang, Kuang-Hsiung Chen, Yu-Ying Lee
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Patent number: 10854550Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.Type: GrantFiled: August 22, 2018Date of Patent: December 1, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Sheng-Ming Wang, Tien-Szu Chen, Wen-Chih Shen, Hsing-Wen Lee, Hsiang-Ming Feng
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Patent number: 10734337Abstract: A micro-electromechanical systems (MEMS) package structure includes: (1) a circuit layer; (2) a MEMS die with an active surface, wherein the active surface faces the circuit layer; (3) a conductive pillar adjacent to the MEMS die; and (4) a package body encapsulating the MEMS die and the conductive pillar, and exposing a top surface of the conductive pillar.Type: GrantFiled: March 5, 2019Date of Patent: August 4, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Kuang-Hsiung Chen, Yu-Hsuan Tsai, Yu-Ying Lee, Sheng-Ming Wang, Wun-Jheng Syu
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Patent number: 10629519Abstract: A semiconductor device package includes an electronic device, a conductive frame and a first molding layer. The conductive frame is disposed over and electrically connected to the electronic device, and the conductive frame includes a plurality of leads. The first molding layer covers the electronic device and a portion of the conductive frame, and is disposed between at least two adjacent ones of the leads.Type: GrantFiled: November 29, 2016Date of Patent: April 21, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tien-Szu Chen, Sheng-Ming Wang, I-Cheng Wang, Wun-Jheng Syu
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Patent number: 10573624Abstract: A semiconductor device package includes: (1) a first circuit layer including a first surface and a second surface opposite to the first surface; (2) at least one electrical element disposed over the first surface of the first circuit layer and electrically connected to the first circuit layer; (3) a first molding layer disposed over the first surface of the first circuit layer, wherein the first molding layer encapsulates an edge of the at least one electrical element; (4) first electronic components disposed over the second surface of the first circuit layer and electrically connected to the first circuit layer; and (5) a second molding layer disposed over the second surface of the first circuit layer and encapsulating the first electronic components, wherein the first molding layer and the second molding layer include different molding materials.Type: GrantFiled: November 16, 2018Date of Patent: February 25, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, I-Cheng Wang, Wun-Jheng Syu
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Patent number: 10515884Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure, a dielectric structure and a metal bump. The conductive structure has a first conductive surface and a second conductive surface. The dielectric structure has a first dielectric surface and a second dielectric surface. The first conductive surface does not protrude from the first dielectric surface. The second conductive surface is recessed from the second dielectric surface. The metal bump is disposed in a dielectric opening of the dielectric structure, and is physically and electrically connected to the second conductive surface. The metal bump has a concave surface.Type: GrantFiled: February 17, 2015Date of Patent: December 24, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, Yu-Ying Lee, Li-Chuan Tsai, Chih-Cheng Lee
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Patent number: 10446411Abstract: A semiconductor package includes: (1) a substrate; (2) a first isolation layer disposed on the substrate, the first isolation layer including an opening; (3) a pad disposed on the substrate and exposed from the opening; (4) an interconnection layer disposed on the pad; and (5) a conductive post including a bottom surface, the bottom surface having a first part disposed on the interconnection layer and a plurality of second parts disposed on the first isolation layer.Type: GrantFiled: August 13, 2018Date of Patent: October 15, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, Yu-Ying Lee, Yu-Tzu Peng
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Publication number: 20190198469Abstract: A micro-electromechanical systems (MEMS) package structure includes: (1) a circuit layer; (2) a MEMS die with an active surface, wherein the active surface faces the circuit layer; (3) a conductive pillar adjacent to the MEMS die; and (4) a package body encapsulating the MEMS die and the conductive pillar, and exposing a top surface of the conductive pillar.Type: ApplicationFiled: March 5, 2019Publication date: June 27, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Kuang-Hsiung CHEN, Yu-Hsuan TSAI, Yu-Ying LEE, Sheng-Ming WANG, Wun-Jheng SYU
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Patent number: 10332851Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a carrier having a first surface and including a power layer adjacent to the first surface of the carrier, an electrical component disposed on the first surface of the carrier, and a conductive element disposed on the first surface of the carrier. The electrical component is electrically connected to the power layer. The conductive element is electrically connected to the power layer. The conductive element, the power layer, and the electrical component form a power-transmission path.Type: GrantFiled: June 22, 2017Date of Patent: June 25, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chung-Chieh Yang, Sheng-Ming Wang, Tien-Szu Chen
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Publication number: 20190096814Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.Type: ApplicationFiled: August 22, 2018Publication date: March 28, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Sheng-Ming WANG, Tien-Szu CHEN, Wen-Chih SHEN, Hsing-Wen LEE, Hsiang-Ming FENG
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Publication number: 20190088626Abstract: A semiconductor device package includes: (1) a first circuit layer including a first surface and a second surface opposite to the first surface; (2) at least one electrical element disposed over the first surface of the first circuit layer and electrically connected to the first circuit layer; (3) a first molding layer disposed over the first surface of the first circuit layer, wherein the first molding layer encapsulates an edge of the at least one electrical element; (4) first electronic components disposed over the second surface of the first circuit layer and electrically connected to the first circuit layer; and (5) a second molding layer disposed over the second surface of the first circuit layer and encapsulating the first electronic components, wherein the first molding layer and the second molding layer include different molding materials.Type: ApplicationFiled: November 16, 2018Publication date: March 21, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Tien-Szu CHEN, Kuang-Hsiung CHEN, Sheng-Ming WANG, I-Cheng WANG, Wun-Jheng SYU