Patents by Inventor Sheng-Ming Wang
Sheng-Ming Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955535Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed below the upper portion of the dielectric feature.Type: GrantFiled: July 26, 2022Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hao Chang, Lin-Yu Huang, Sheng-Tsung Wang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
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Patent number: 11950428Abstract: A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and conductive pillars. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure.Type: GrantFiled: August 9, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chen Wang, Meng-Han Lin, Sai-Hooi Yeong, Yu-Ming Lin, Han-Jong Chia
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Publication number: 20240097010Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Inventors: Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen
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Publication number: 20240098959Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.Type: ApplicationFiled: November 22, 2023Publication date: March 21, 2024Inventors: Kai-Hsuan Lee, Chia-Ta Yu, Cheng-Yu Yang, Sheng-Chen Wang, Sai-Hooi Yeong, Feng-Cheng Yang, Yen-Ming Chen
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Patent number: 11894308Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.Type: GrantFiled: December 1, 2020Date of Patent: February 6, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Sheng-Ming Wang, Tien-Szu Chen, Wen-Chih Shen, Hsing-Wen Lee, Hsiang-Ming Feng
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Publication number: 20210091006Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.Type: ApplicationFiled: December 1, 2020Publication date: March 25, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Sheng-Ming WANG, Tien-Szu CHEN, Wen-Chih SHEN, Hsing-Wen LEE, Hsiang-Ming FENG
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Patent number: 10879159Abstract: A substrate, a semiconductor package thereof and a process of making the same are provided. The substrate comprises an upper circuit layer and a lower circuit layer, the upper circuit layer comprising at least one trace and at least one pad and the lower circuit layer comprising at least one trace and at least one pad, wherein the trace of the upper circuit layer and the trace of the lower circuit layer are not aligned.Type: GrantFiled: May 5, 2015Date of Patent: December 29, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tien-Szu Chen, Sheng-Ming Wang, Kuang-Hsiung Chen, Yu-Ying Lee
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Patent number: 10854550Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.Type: GrantFiled: August 22, 2018Date of Patent: December 1, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Sheng-Ming Wang, Tien-Szu Chen, Wen-Chih Shen, Hsing-Wen Lee, Hsiang-Ming Feng
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Patent number: 10734337Abstract: A micro-electromechanical systems (MEMS) package structure includes: (1) a circuit layer; (2) a MEMS die with an active surface, wherein the active surface faces the circuit layer; (3) a conductive pillar adjacent to the MEMS die; and (4) a package body encapsulating the MEMS die and the conductive pillar, and exposing a top surface of the conductive pillar.Type: GrantFiled: March 5, 2019Date of Patent: August 4, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Kuang-Hsiung Chen, Yu-Hsuan Tsai, Yu-Ying Lee, Sheng-Ming Wang, Wun-Jheng Syu
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Patent number: 10629519Abstract: A semiconductor device package includes an electronic device, a conductive frame and a first molding layer. The conductive frame is disposed over and electrically connected to the electronic device, and the conductive frame includes a plurality of leads. The first molding layer covers the electronic device and a portion of the conductive frame, and is disposed between at least two adjacent ones of the leads.Type: GrantFiled: November 29, 2016Date of Patent: April 21, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tien-Szu Chen, Sheng-Ming Wang, I-Cheng Wang, Wun-Jheng Syu
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Patent number: 10573624Abstract: A semiconductor device package includes: (1) a first circuit layer including a first surface and a second surface opposite to the first surface; (2) at least one electrical element disposed over the first surface of the first circuit layer and electrically connected to the first circuit layer; (3) a first molding layer disposed over the first surface of the first circuit layer, wherein the first molding layer encapsulates an edge of the at least one electrical element; (4) first electronic components disposed over the second surface of the first circuit layer and electrically connected to the first circuit layer; and (5) a second molding layer disposed over the second surface of the first circuit layer and encapsulating the first electronic components, wherein the first molding layer and the second molding layer include different molding materials.Type: GrantFiled: November 16, 2018Date of Patent: February 25, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, I-Cheng Wang, Wun-Jheng Syu
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Patent number: 10515884Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure, a dielectric structure and a metal bump. The conductive structure has a first conductive surface and a second conductive surface. The dielectric structure has a first dielectric surface and a second dielectric surface. The first conductive surface does not protrude from the first dielectric surface. The second conductive surface is recessed from the second dielectric surface. The metal bump is disposed in a dielectric opening of the dielectric structure, and is physically and electrically connected to the second conductive surface. The metal bump has a concave surface.Type: GrantFiled: February 17, 2015Date of Patent: December 24, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, Yu-Ying Lee, Li-Chuan Tsai, Chih-Cheng Lee
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Patent number: 10446411Abstract: A semiconductor package includes: (1) a substrate; (2) a first isolation layer disposed on the substrate, the first isolation layer including an opening; (3) a pad disposed on the substrate and exposed from the opening; (4) an interconnection layer disposed on the pad; and (5) a conductive post including a bottom surface, the bottom surface having a first part disposed on the interconnection layer and a plurality of second parts disposed on the first isolation layer.Type: GrantFiled: August 13, 2018Date of Patent: October 15, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, Yu-Ying Lee, Yu-Tzu Peng
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Publication number: 20190198469Abstract: A micro-electromechanical systems (MEMS) package structure includes: (1) a circuit layer; (2) a MEMS die with an active surface, wherein the active surface faces the circuit layer; (3) a conductive pillar adjacent to the MEMS die; and (4) a package body encapsulating the MEMS die and the conductive pillar, and exposing a top surface of the conductive pillar.Type: ApplicationFiled: March 5, 2019Publication date: June 27, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Kuang-Hsiung CHEN, Yu-Hsuan TSAI, Yu-Ying LEE, Sheng-Ming WANG, Wun-Jheng SYU
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Patent number: 10332851Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a carrier having a first surface and including a power layer adjacent to the first surface of the carrier, an electrical component disposed on the first surface of the carrier, and a conductive element disposed on the first surface of the carrier. The electrical component is electrically connected to the power layer. The conductive element is electrically connected to the power layer. The conductive element, the power layer, and the electrical component form a power-transmission path.Type: GrantFiled: June 22, 2017Date of Patent: June 25, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chung-Chieh Yang, Sheng-Ming Wang, Tien-Szu Chen
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Publication number: 20190096814Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.Type: ApplicationFiled: August 22, 2018Publication date: March 28, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Sheng-Ming WANG, Tien-Szu CHEN, Wen-Chih SHEN, Hsing-Wen LEE, Hsiang-Ming FENG
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Publication number: 20190088626Abstract: A semiconductor device package includes: (1) a first circuit layer including a first surface and a second surface opposite to the first surface; (2) at least one electrical element disposed over the first surface of the first circuit layer and electrically connected to the first circuit layer; (3) a first molding layer disposed over the first surface of the first circuit layer, wherein the first molding layer encapsulates an edge of the at least one electrical element; (4) first electronic components disposed over the second surface of the first circuit layer and electrically connected to the first circuit layer; and (5) a second molding layer disposed over the second surface of the first circuit layer and encapsulating the first electronic components, wherein the first molding layer and the second molding layer include different molding materials.Type: ApplicationFiled: November 16, 2018Publication date: March 21, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Tien-Szu CHEN, Kuang-Hsiung CHEN, Sheng-Ming WANG, I-Cheng WANG, Wun-Jheng SYU
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Patent number: 10224298Abstract: In one or more embodiments, a micro-electromechanical systems (MEMS) package structure comprises a MEMS die, a conductive pillar adjacent to the MEMS die, a package body and a binding layer on the package body. The package body encapsulates the MEMS die and the conductive pillar, and exposes a top surface of the conductive pillar. A glass transition temperature (Tg) of the package body is greater than a temperature for forming the binding layer (Tc).Type: GrantFiled: July 13, 2017Date of Patent: March 5, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Kuang-Hsiung Chen, Yu-Hsuan Tsai, Yu-Ying Lee, Sheng-Ming Wang, Wun-Jheng Syu
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Publication number: 20180374811Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a carrier having a first surface and including a power layer adjacent to the first surface of the carrier, an electrical component disposed on the first surface of the carrier, and a conductive element disposed on the first surface of the carrier. The electrical component is electrically connected to the power layer. The conductive element is electrically connected to the power layer. The conductive element, the power layer, and the electrical component form a power-transmission path.Type: ApplicationFiled: June 22, 2017Publication date: December 27, 2018Inventors: Chung-Chieh YANG, Sheng-Ming WANG, Tien-Szu CHEN
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Patent number: 10157887Abstract: A semiconductor device package includes a first circuit layer, at least one electrical element, a first molding layer, an electronic component and a second molding layer. The at least one electrical element is disposed over a first surface of the first circuit layer and electrically connected to the first circuit layer. The first molding layer is disposed over the first surface of the first circuit layer. The first molding layer encapsulates an edge of the at least one electrical element, and a lower surface of the first molding layer and a lower surface of the at least one electrical element are substantially coplanar. The electronic component is disposed over a second surface of the first circuit layer and is electrically connected to the first circuit layer. The second molding layer is disposed over the second surface of the first circuit layer and encapsulates the electronic component.Type: GrantFiled: March 9, 2017Date of Patent: December 18, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, I-Cheng Wang, Wun-Jheng Syu