Patents by Inventor Sheng-Ming Wang

Sheng-Ming Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160079194
    Abstract: A semiconductor substrate includes an insulating layer, a first conductive patterned layer disposed adjacent to a first surface of the insulating layer, and conductive bumps disposed on the first conductive patterned layer. Each conductive bump has a first dimension along a first direction and a second dimension along a second direction perpendicular to the first direction, and the first dimension is greater than the second dimension. A semiconductor package structure includes the semiconductor substrate, at least one die electrically connected to the conductive bumps, and a molding compound encapsulating the conductive bumps.
    Type: Application
    Filed: September 16, 2015
    Publication date: March 17, 2016
    Inventors: Tien-Szu Chen, Sheng-Ming Wang, Kuang-Hsiung Chen, Yu-Ying Lee
  • Patent number: 9224707
    Abstract: A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: December 29, 2015
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Chun-Che Lee, Sheng-Ming Wang
  • Publication number: 20150318235
    Abstract: A substrate, a semiconductor package thereof and a process of making the same are provided. The substrate comprises an upper circuit layer and a lower circuit layer, the upper circuit layer comprising at least one trace and at least one pad and the lower circuit layer comprising at least one trace and at least one pad, wherein the trace of the upper circuit layer and the trace of the lower circuit layer are not aligned.
    Type: Application
    Filed: May 5, 2015
    Publication date: November 5, 2015
    Inventors: Tien-Szu CHEN, Sheng-Ming WANG, Kuang-Hsiung CHEN, Yu-Ying LEE
  • Patent number: 9054118
    Abstract: An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices is attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: June 9, 2015
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuang-Hsiung Chen, Sheng-Ming Wang, Yu-Ying Lee, Hsiang-Ming Feng, Bing-Yun Cheng
  • Publication number: 20150048002
    Abstract: The present invention discloses a beverage container 13, having a circular upper orifice for receiving a removable threaded cap to contain a carbonated drink, a beverage container 10, having a donut shape upper orifice for receiving a removable donut shape seal of aluminum foil to contain a mixed juice, the beverage container 10 nesting on top of the beverage container 13, the removable threaded cap keeping the two nested beverage containers interlocked, and a desired cocktail punch produced through mixing the carbonated drink and juice inside the beverage container 13.
    Type: Application
    Filed: August 15, 2013
    Publication date: February 19, 2015
    Inventor: Sheng Ming Wang
  • Publication number: 20150021766
    Abstract: A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.
    Type: Application
    Filed: October 8, 2014
    Publication date: January 22, 2015
    Inventors: Tien-Szu Chen, Chun-Che Lee, Sheng-Ming Wang
  • Patent number: 8884443
    Abstract: A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: November 11, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Tien-Szu Chen, Chun-Che Lee, Sheng-Ming Wang
  • Publication number: 20140327125
    Abstract: A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate strip comprising a plurality of substrate units; disposing a plurality of chips on the plurality of substrate units; disposing a packaging encapsulant on the substrate strip to encapsulate the chips; forming a warp-resistant layer on a top surface of the packaging encapsulant; and dividing the substrate strip to separate the plurality of substrate units to further fabricate a plurality of semiconductor package structures, wherein the warp-resistant layer is formed of a selected material with a selected thickness to make a variation of warpage of the semiconductor package structure at a temperature between 25° C. and 260° C. to be smaller than 560 ?m.
    Type: Application
    Filed: May 2, 2014
    Publication date: November 6, 2014
    Inventors: Tien-Szu CHEN, Sheng-Ming WANG, Kuang-Hsiung CHEN, Yu-Ying LEE
  • Patent number: 8866311
    Abstract: The substrate includes a first dielectric layer, a first circuit pattern, a plurality of pillars and a second circuit pattern. The first dielectric layer has opposing first and second dielectric surfaces. The first circuit pattern is embedded in the first dielectric layer and defines a plurality of curved trace surfaces. Each of the pillars has an exterior surface adapted for making external electrical connection and a curved base surface abutting a corresponding one of the trace surfaces. The second circuit pattern is on the second dielectric surface of the first dielectric layer and electrically connected to the first circuit pattern.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: October 21, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, Hsiang-Ming Feng, Yen-Hua Kuo
  • Publication number: 20140308778
    Abstract: An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices is attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.
    Type: Application
    Filed: June 24, 2014
    Publication date: October 16, 2014
    Inventors: Kuang-Hsiung Chen, Sheng-Ming Wang, Yu-Ying Lee, Hsiang-Ming Feng, Bing-Yun Cheng
  • Patent number: 8779581
    Abstract: An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices are attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: July 15, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuang-Hsiung Chen, Sheng-Ming Wang, Yu-Ying Lee, Hsiang-Ming Feng, Bing-Yun Cheng
  • Patent number: 8686568
    Abstract: The package substrate includes a core, a plurality of first circuit segments, and a plurality of conductive pillars. Each of the first circuit segments has a patterned metal layer disposed on the core, a barrier layer disposed on the patterned metal layer, and an upper metal pattern disposed on the barrier layer. The conductive pillars penetrate the core, the patterned metal layer, and the barrier layer, and contact the upper metal pattern. The conductive pillars are formed from a material that can be selectively removed without affecting the barrier layer.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: April 1, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Sheng-Ming Wang, Hsiang-Ming Feng, Yen-Hua Kuo
  • Publication number: 20140084480
    Abstract: The package substrate includes a core, a plurality of first circuit segments, and a plurality of conductive pillars. Each of the first circuit segments has a patterned metal layer disposed on the core, a barrier layer disposed on the patterned metal layer, and an upper metal pattern disposed on the barrier layer. The conductive pillars penetrate the core, the patterned metal layer, and the barrier layer, and contact the upper metal pattern. The conductive pillars are formed from a material that can be selectively removed without affecting the barrier layer.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Sheng-Ming Wang, Hsiang-Ming Feng, Yen-Hua Kuo
  • Publication number: 20140084475
    Abstract: The substrate includes a first dielectric layer, a first circuit pattern, a plurality of pillars and a second circuit pattern. The first dielectric layer has opposing first and second dielectric surfaces. The first circuit pattern is embedded in the first dielectric layer and defines a plurality of curved trace surfaces. Each of the pillars has an exterior surface adapted for making external electrical connection and a curved base surface abutting a corresponding one of the trace surfaces. The second circuit pattern is on the second dielectric surface of the first dielectric layer and electrically connected to the first circuit pattern.
    Type: Application
    Filed: September 21, 2012
    Publication date: March 27, 2014
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, Hsiang-Ming Feng, Yen-Hua Kuo
  • Publication number: 20140008814
    Abstract: A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.
    Type: Application
    Filed: May 16, 2013
    Publication date: January 9, 2014
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Chun-Che Lee, Sheng-Ming Wang
  • Patent number: 8592962
    Abstract: A Quad Flat No Leads (QFN) package includes a lead frame, a chip, an encapsulant, and a protective layer. The lead frame includes a plurality of leads. Each of the leads has a lower surface that is divided into a contact area and a non-contact area. The chip is configured on and electrically connected to the lead frame. The encapsulant encapsulates the chip and the leads and fills spaces between the leads. The contact areas and the non-contact areas of the leads are exposed by the encapsulant. The protective layer covers the non-contact areas of the leads.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: November 26, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuang-Hsiung Chen, Sheng-Ming Wang, Hsiang-Ming Feng, Yu-Ying Lee, Mei-Lin Hsieh
  • Publication number: 20120168400
    Abstract: A beverage container made of plastic by blow molding process has three chambers all along a same axis—an upper conical chamber with a removable cap to contain carbon dioxide gas (but not limited to), a lower outer cylindrical chamber, connected to the upper conical chamber, to contain a carbonated drink (but not limited to), and an inner cylindrical open chamber, smaller in diameter & height than the lower outer cylindrical chamber and isolated from the two other chambers, to store a sealed cylindrical tube containing a pasteurized drink (but not limited to). A liquid ratio of the carbonated drink to the pasteurized drink is the ratio of an optimum mixture of the two beverages into a certain desired cocktail punch. At the time of bottling, the sealed cylindrical tube containing the pasteurized drink will be inserted into the frictionally fitted inner cylindrical open chamber, then the other two chambers will be filled with the carbon dioxide and the carbonated drink accordingly and capped.
    Type: Application
    Filed: December 30, 2010
    Publication date: July 5, 2012
    Inventor: Sheng-Ming Wang
  • Publication number: 20120112338
    Abstract: An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices are attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.
    Type: Application
    Filed: November 7, 2011
    Publication date: May 10, 2012
    Inventors: Kuang-Hsiung Chen, Sheng-Ming Wang, Yu-Ying Lee, Hsiang-Ming Feng, Bing-Yun Cheng
  • Publication number: 20120104584
    Abstract: A Quad Flat No Leads (QFN) package includes a lead frame, a chip, an encapsulant, and a protective layer. The lead frame includes a plurality of leads. Each of the leads has a lower surface that is divided into a contact area and a non-contact area. The chip is configured on and electrically connected to the lead frame. The encapsulant encapsulates the chip and the leads and fills spaces between the leads. The contact areas and the non-contact areas of the leads are exposed by the encapsulant. The protective layer covers the non-contact areas of the leads.
    Type: Application
    Filed: August 29, 2011
    Publication date: May 3, 2012
    Inventors: Kuang-Hsiung Chen, Sheng-Ming Wang, Hsiang-Ming Feng, Yu-Ying Lee, Mei-Lin Hsieh
  • Patent number: 7637129
    Abstract: A washing machine having high pressure angled air jets that introduce air into the wash water in a stationary pressurized tub. A circular swirl flow-pattern and air pressure within the warm wash water agitates and cleans the clothes without the need for a mechanically rotated drum or detergent. Sediment from the laundry is removed from the water by drains both at the top and the bottom of the tub. At the end of the wash cycle, the high pressure air is used to drain and dehydrate the clean clothes.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: December 29, 2009
    Inventor: Sheng-Ming Wang