Sheng T. Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: A coil module is provided, including a second coil mechanism. The second coil mechanism includes a third coil assembly and a second base corresponding to the third coil assembly. The second base has a positioning assembly corresponding to a first coil mechanism.
Abstract: A method is provided for improving the electrical isolation between surface regions and underlying support regions in SIMOX buried oxide wafers. The method implants nitrogen ions into a wafer to approximately the same depth as oxygen ions are implanted during SIMOX processing. A subsequent heating step causes the nitrogen ions to migrate to the interface region between the buried oxide and the upper and lower semiconductor regions of the substrate. The nitrogen passivates the interface regions to reduce the presence of buried free electrons trapped in the substrate. Nitrogen implantation can be performed before, during, or after the oxygen is implanted. Nitrogen ions can also be implanted after the SIMOX buried silicon dioxide layer has been formed. If the latter alternative is followed, the wafer must be subsequently heated to migrate the nitrogen ions to the interface regions within the substrate. Such subsequent heating can be performed as part of the formation of devices on the substrate.
Abstract: A self-aligned multi-level interconnect structure and a method for fabricating the same are disclosed. The multi-level interconnect structure is fabricated by the steps of: (1) forming a first plurality of spaced-apart insulative layers [231-233], where the first plurality includes a top insulative layer ; (2) forming a second plurality of spaced-apart conductors [221,222] and positioning them interdigitally between the insulative layers; (3) defining a first hole [233h] extending through the top insulative layer ; (4) using the first hole [233h] to define a succession of self-aligned subsequent holes [222h,232h,22ih,231h] through the underlying conductors and insulative layers, each successive hole being continuous with and self-aligned to one above it; and (5) defining a through-conductor  extending through the succession of self-aligned holes. The self-aligned multi-level interconnect structure is employed in a multi-layer SRAM cell.
Abstract: A BiCMOS structure in which the bipolar transistor is preferably arranged vertically and the MOS transistors are formed on insulator. SIMOX techniques may be used to form a starting substrate.
Abstract: A process is disclosed for forming bipolar transistors in a BiCMOS process which is fully compatible with the CMOS process used to form other devices in the same integrated circuit. The process produces bipolar transistor sizes which are compatible with the minimum size features and design rules of the CMOS process. A CVD silicon oxide layer to be used to form spacers is deposited on the top of emitter and gate electrodes covered with a first oxide layer.
Abstract: A structure and method for making a pair of MOS field effect transistors (MOSFETs), one stacked upon the other in an integrated circuit device is disclosed. In one embodiment of the device, the active layer of the upper MOSFET is epitaxially grown from an exposed surface of the active layer of the lower MOSFET. In another embodiment, the active layer of the upper MOSFET is polysilicon which, optionally, may be recrystallized. In all embodiments, the pair of MOSFETs share a common gate.
Abstract: The area of a BiCMOS integrated circuit is reduced by fabricating portions of the MOS transistor within the bipolar transistor. A BiCMOS integrated inverter circuit having a 35% reduction in area is disclosed.
Abstract: A CMOS device having shallow source and drain regions is formed in a body of single crystalline silicon having a major surface by forming in the body adjacent well regions of opposite conductivity type having an isolation region of an insulating material extending into the body from the major surface along the junction of the well regions. Thin layers of silicon oxide are formed on the major surface over each of the well regions, and a gate line of conductive polycrystalline silicon is formed over each of the silicon oxide layers. The side walls of the gate lines are covered with a layer of silicon oxide. A layer of polycrystalline silicon is selectively deposited on the surface of the body at each side of each gate line and on the gate lines. A layer of a refractory metal is deposited on the polycrystalline silicon layer. The polycrystalline silicon layer is heated to cause the metal to react with the silicon and form a metal silicide region at least partially through the polycrystalline silicon layer.
Abstract: A method of making a MOS transistor having source and drain extensions includes forming on a surface of a substrate of single crystalline silicon a gate line having a thin layer of silicon oxide between the gate line and the substrate surface. A light dose of ions of a desired conductivity type are embedded in the substrate surface at each side of the gate line up to the side walls of the gate line. Spacers of thermally grown silicon oxide are formed on the side walls of the gate line and a dose of the ions of the desired conductivity type are embedded into the substrate surface at each side of the gate line to form source and drain regions. The source and drain regions extend up to the spacers and have lightly doped extensions extending up to the side walls of the gate line under the spacers.
Abstract: A semiconductor device and method of making is disclosed wherein the semiconductor device includes a MOSFET with very shallow source and drain regions. The high sheet resistivity normally associated with such shallow regions is obviated by growing an epitaxial layer directly from the surface of the shallow source and drain regions, highly doping the layer, then forming a layer of refractory metal silicide on the epitaxial layer. The resulting structure yields a MOSFET having very shallow source and drain regions with very low sheet resistance.
Abstract: An N-channel transistor formed in a layer of semiconductor material disposed on a insulating substrate is disclosed. The source region has a depth less than the thickness of the semiconductor layer so that a P-type region can be formed in the semiconductor layer between the source region and the insulating substrate. This P-type region has an impurity concentration sufficient to prevent the depletion region of the source from extending to the interface between the layer of semiconductor material and the substrate. The P-type region substantially prevents back-channel leakage currents from flowing between the source region and the drain region along the portion of the layer of semiconductor material immediately adjacent the insulating substrate when the device has been irradiated.
Abstract: A method for fabricating an integrated circuit including at least one metal-oxide-semiconductor transistor (MOS) and at least one bipolar transistor is disclosed. The pocket regions used to reduce the short channel effect in the MOS transistor are formed simultaneously with the base region for the bipolar transistor.
Abstract: An array of electrically alterable floating gate devices arranged in rows and columns with each column of devices sharing a column conductor. Each row of devices is connected between two row conductors with adjacent rows sharing a common row conductor whereby in an array having N rows of devices there is a total of (N+1) row conductors. Input and output decoders connected to the row conductors enable the unique read-out of any selected element.
Abstract: A semiconductor device includes a substrate of single crystalline silicon having the active regions of a semiconductor element, such as the source, drain, channel and gates, along one surface of the substrate, and a thin gettering region of a gettering material in the substrate. The gettering region is spaced from both surfaces of the substrate and is adjacent the active regions of the semiconductor element so as to getter contaminants in the substrate from the area of the substrate containing the semiconductor element.
Abstract: A method of forming a semiconductor device is disclosed wherein the doping concentration of the side wall of a trench isolation region is increased. An opening is formed in a first masking layer so as to expose a portion of the semiconductor substrate. Then, dopants are introduced through the opening in the masking layer so as to form a heavily doped region within the semiconductor substrate. An isolation trench is then formed in the exposed portion of the semiconductor substrate. At least a portion of the side wall of the trench is located in the heavily doped region. The heavily doped region increases the threshold voltage of the side wall transistor and thereby reduces the leakage current along the side wall of the trench isolation region.
Abstract: A method of exposing only the top surface of a narrow mesa is disclosed wherein a protective layer may be very precisely formed on a very narrow mesa for subsequent doping of areas adjacent the mesa without doping the mesa itself. A variation of the invention includes forming an opening directly over the narrow mesa so that a contact may be made at only the top surface of the mesa or the upper portion of the mesa may be doped independent of surfaces adjacent the mesa.
Abstract: A multi-level metallization is formed by forming a patterned first level metallization layer on the surface of an isolating layer on a substrate of semiconductor material. A thick planarizing layer, preferably of a glass, is applied over the first level metallization layer and the exposed areas of the insulating layer with the planarizing layer bearing depressions in its surface over the exposed areas of the insulating layer. A photoresist layer is formed on the planarizing layer in the depressions in its surface with the portions of the planarizing layer over the first level metallization layer being exposed. The exposed areas of the planarizing layer are isotropically etched until the surface of the planarizing layer is substantially planar with the bottom of the deepest depression in the planarizing layer. Any photoresist material is removed and the planarizing layer is isotropically etched until its surface is substantially planar with the surface of the first level metallization layer.
August 5, 1985
Date of Patent:
May 5, 1987
Sheng T. Hsu, Doris W. Flatley, Ronald J. Johansson
Abstract: A method for making a MOS field effect transistor structure having tungsten silicide contact surfaces for the gate and source and drain regions is disclosed. Protective oxide is very precisely positioned so that a tungsten layer is formed on only selected silicon surfaces by selective deposition. Next, a layer of polysilicon is formed on said tungsten layer. The resulting structure is treated in an oxygen atmosphere to form the desired tungsten silicide. A silicon nitride cap can also be used to cover the gate portion during source and drain formation.
Abstract: The ion implantation of a silicon structure isolated from a semiconductor substrate by a layer of silicon dioxide with boron ions to render it p type conductive is improved by initially doping the silicon with phosphorus ions. The presence of the phosphorus ions in the silicon prevents the implanted boron ions from rapidly migrating into the silicon dioxide during annealing.
Abstract: In order to reduce the mechanical stress that occurs at the interface of a layer of a refractory metal silicide and a layer of silicon dioxide, it is proposed that a buffer layer of polycrystalline silicon be interposed between the two layers. To accomplish this and prior to forming contact openings, the buffer layer of polycrystalline silicon is deposited on the layer of silicon dioxide and the structure is then provided with an apertured mask to define the contact openings. The structure is then initially etched through both the buffer layer and the underlying layer of silicon dioxide in order to expose portions of the buried contact regions followed by a second etch of only the buffer layer to only expose portions of the layer of silicon dioxide in order to form a gate member and any required interconnects. The process further includes the formation of a layer of metal silicide on the interconnects, in the contact openings and on the gate member.