Abstract: A novel process for fabricating low resistance contacts for high density integrated circuits is described wherein during the initial processing of the device, after a scaled MOSFET is formed, contact openings, having vertical walls with respect to the underlying substrate, are provided. An apertured masking layer, having apertures which provide an open are a somewhat larger than the original contact opening, is formed on the structure after which, the structure is subjected to a high energy deep implant step followed by a low energy, shallow, supplemental implant step. The high energy implant serves to provide the device with a deep junction at the contact area to minimize spiking and, by reason of the shallow implant, good ohmic contact may be made. Since the oxide surrounding the contact opening is also implanted, there is provided means for tapering the edges of the contact opening.

Abstract: A memory array formed on a single chip is provided with at least one redundant column (or row) of memory cells in addition to "standard" number of columns and rows where the spare column (or row) of cells is designed to be substituted for a standard column (or row) found to have defective cells. Programmable non-volatile electrically alterable elements are connected to the column (or rows) conductors of the standard and redundant columns (or rows) of cells for selectively disconnecting from the memory circuit a standard column (or rows) containing defective cells and substituting therefor a redundant column (or row) of cells.

Abstract: A process for defining improved tapered contact openings in glass coatings comprising the deposition of a layer of low temperature flowable passivating glass and the deposition of a masking layer to initially approximately define contact areas over portions of the active regions and over portions of a gate line. The first contact openings are then etched and the passivating layer caused to reflow followed by a second etch, in the previously etched areas, which second etch accurately defines the contact openings. The final etch rounds off any corners produced by the second etch to produce smoothly tapered contact openings. .circle.

Abstract: A method of forming buried contacts that eliminates the possibility of the inadvertent removal of portions of the silicon body is described wherein a patterned nitride masking layer is formed on portions of conductive interconnects and gate lines. Thereafter, a second oxide layer is grown in order to surround the masking nitride layer. The nitride layer may now be easily removed using a hot phosphoric acid dip which will etch away only the nitride layer to form contact openings in the oxide layer without affecting the underlying layer.

Abstract: A process for defining improved tapered openings in glass coatings requires that passivating layers be formed of a doped silicon oxide having a relatively low flow temperature formed on a layer of undoped silicon oxide. After the contact openings are formed, both oxide layers are heated to a temperature below the flow temperature of the doped layer for a period of time sufficient to only soften and partially reflow the doped layer, the temperature being insufficient to form a significant oxide growth on the exposed portion of the semiconductor body.

Abstract: An improved gate injected, floating gate memory device is described having improved charge retention and endurance characteristics is described in which the barrier height for the injection of charge (electrons or holes) into the floating gate is reduced. This is accomplished by utilizing a layer of semi-insulating polycrystalline silicon between the control electrode and the insulating layer over the floating gate.

Abstract: A non-volatile memory structure of the floating gate type is described wherein current carriers are injected onto the floating gate from the control gate as distinguished from the prior art which injects current carriers into the floating gate from the substrate. This invention teaches that by tailoring the capacitance between the control gate and the floating gate and the capacitance between the floating gate and the substrate different field intensities are created in the region between the floating gate and the control gate and in the region between the substrate and the floating gate. When the field intensity across the capacitor formed between the control gate and the floating gate is greater than the field intensity across the capacitor formed between the floating gate and the substrate, current carriers will be injected onto the floating gate from the control gate.

Abstract: A Metal-Oxide-Semiconductor-Field Effect Transistor (MOSFET) is described wherein a body of semiconductor material is provided with source, drain and channel regions. A gate structure is provided over the interstitial channel region of the semiconductor body between the drain and source regions, one edge of which is aligned with the source region. The remainder of the channel region, between the other edge of the gate structure and the adjacent edge of the drain region is provided with a drift region of a conductivity type that is the same as the source and drain.

Abstract: The conduction path of a first transistor means of first conductivity type is connected between a first point of operating potential and an output point. The conduction paths of second and third transistors of second conductivity type are connected in series between the output point and a second point of operating potential. An input signal is applied to the gate electrode of the third transistor while a control voltage is applied to the gate electrodes of the first and second transistors. Different values of control voltage are applied to operate the circuit in different modes. For a control voltage equal to the voltage at the first point the circuit can function to clamp the output to the second point. For a control voltage equal to the voltage at the second point the circuit can function to couple the output to the first point.

Abstract: Two matrix arrays comprised of Gate Injected Metal Oxide Semiconductor (GIMOS) non-volatile memory elements. Interconnection is made via inverters to form an electrically Alterable Programmable Logic Array (ALPLA).

Abstract: A short channel insulated gate field effect transistor, suitable for use in high speed integrated circuits is described as being manufactured by a self-aligned process in which the gate electrode is formed by a selective etching technique. In practicing the process, an etch limiting element is laterally diffused from an adjacent solid source into a polycrystalline silicon layer. In one embodiment, a portion of the solid source serves as a mask in another step of the process to define the length of a drain extension region.

Abstract: A non-volatile memory structure of the floating gate type is described wherein current carriers are injected onto the floating gate from the control gate as distinguished from the prior art which injects current carriers into the floating gate from the substrate. This invention teaches that by tailoring the capacitance between the control gate and the floating gate and the capacitance between the floating gate and the substrate different field intensities are created in the region between the floating gate and the control gate and in the region between the substrate and the floating gate. When the field intensity across the capacitor formed between the control gate and the floating gate is greater than the field intensity across the capacitor formed between the floating gate and the substrate, current carriers will be injected onto the floating gate from the control gate.

Abstract: The method presented may be utilized in manufacturing CMOS integrated circuits either in an isoplanar or in a LOCOS process. The method entails the simultaneous formation of the well region with the oxide isolation regions by a drive-in diffusion which is conducted in a dry oxygen ambient. The utilization of the process insures that compounds of silicon, nitrogen and oxygen will not be present in the bulk silicon where they can effect the quality of gate oxides which are subsequently formed.

Abstract: A novel process is described for forming a gate member for an SOS device wherein the objectionable point that appears at the top of the silicon island is removed. The point results when an anisotropic etch is utilized to form the island. The process includes first forming a relatively thick layer of CVD oxide around sides at the base portion of the island while the remainder of the sides of the island, including the objectionable point, remain exposed for further processing in order to remove the point. The point is then heavily oxidized to form a bird beak which bird beak joins the gate oxide with the CVD oxide to produce a rounded edge.

Abstract: A method for fabricating a complementary MOS device, applicable to either silicon-on-sapphire or bulk silicon, is described wherein a buried contact is formed that is comprised of a region of doped silicon, a layer of MoSi.sub.2, a thin layer of Mo and a layer of doped polycrystalline silicon.

Abstract: An improved gate injected, floating gate memory device is described having improved charge retention and endurance characteristics is described in which the barrier height for the injection of charge (electrons or holes) into the floating gate is reduced. This is accomplished by utilizing a layer of semi-insulating polycrystalline silicon between the control electrode and the insulating layer over the floating gate.

Abstract: A voltage comparator utilizing complementary MOS techniques. The comparator includes a pair of complementary field effect transistors with serial connected channels. A first signal to be compared is applied to the gate of one of the pair of transistors. A second signal is applied to the gate of the pair of transistors such that the transistor pair operates as a quasi-differential amplifier. The output of the transistor pair is subsequently amplified by a cross-coupled latch.

Abstract: The invention is a memory device which includes a metal-nitride-oxide semiconductor (MNOS) insulated gate field effect transistor (IGFET) which is built in series with the base of a bipolar transistor to provide both bipolar current handling capability and bipolar radiation hardness while retaining MNOS memory performance.

Abstract: A Metal-Oxide-Semiconductor-Field Effect Transistor (MOSFET) is described wherein a body of semiconductor material is provided with source, drain and channel regions. A gate structure is provided over the interstitial channel region of the semiconductor body between the drain and source regions, one edge of which is aligned with the source region. The remainder of the channel region, between the other edge of the gate structure and the adjacent edge of the drain region is provided with a drift region of a conductivity type that is opposite to that of the source and drain.

Abstract: A method of making a monolithic semiconductor-on-insulator device which includes silicon islands in spaced relation on the surface of an insulating substrate includes the steps of filling the spaces between the islands with a passivating material by first depositing a layer of a semi-insulating material on the surface of the substrate and extending between adjacent islands into contiguous relation with the side surfaces thereof and then depositing a layer of insulating material on the layer of semi-insulating material. The combined thicknesses of the layers of semi-insulating and insulating material is substantially the same as the thickness of the silicon islands so that the resulting device has a substantially planar surface.