Patents by Inventor Sheng Teng Hsu

Sheng Teng Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200168948
    Abstract: An electrolyte composition, a method of fabricating the same, and an energy storage device with the electrolyte composition are provided. The method of fabricating an electrolyte composition has steps of: mixing a modified polyoxyethylene-based material and a siloxane-based material in a solvent to form a mixture in which a tail end of a group of the modified polyoxyethylene-based material has an amine group; and heating the mixture at a temperature ranging from 50 to 60° C. for a time ranging from 3 to 5 hours for obtaining an electrolyte composition which is formed by bonding the amine group of the modified polyoxyethylene-based material to the siloxane-based material. The electrolyte composition enables conductive ions to conduct in an electrolyte easily.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 28, 2020
    Inventors: Shih-ting HSU, Hsisheng TENG, Sheng-shu HOU, Yu-hsien TSENG, Bo-hsiung WU, Subramani RAMESH, Thanh Binh TRAN, Thi Tuyet Hanh NGUYEN
  • Patent number: 10586902
    Abstract: A light-emitting device includes a light-emitting structure with a side surface, and a reflective layer covering the side surface. The light-emitting structure has a first light-emitting angle and a second light-emitting angle. The difference between the first light-emitting angle and the second light-emitting angle is larger than 15°.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: March 10, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chien-Liang Liu, Ming-Chi Hsu, Shih-An Liao, Chun-Hung Liu, Zhi-Ting Ye, Cheng-Teng Ye, Po-Chang Chen, Sheng-Che Chiou
  • Patent number: 10461331
    Abstract: A lithium battery is provided and has a plurality of graphene oxide quantum dots, where the graphene oxide quantum dots have an average particle size between 2 nm and 9 nm. The graphene oxide quantum dots can improve electrical properties of the lithium battery.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: October 29, 2019
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Yen-Ming Chen, Te-Fu Yeh, Shih-Ting Hsu, Hsisheng Teng, Sheng-Shu Hou, Jeng-Shiung Jan
  • Publication number: 20190172987
    Abstract: A light-emitting device includes a light-emitting structure with a side surface, and a reflective layer covering the side surface. The light-emitting structure has a first light-emitting angle and a second light-emitting angle. The difference between the first light-emitting angle and the second light-emitting angle is larger than 15°.
    Type: Application
    Filed: December 27, 2018
    Publication date: June 6, 2019
    Inventors: Chien-Liang LIU, Ming-Chi HSU, Shih-An LIAO, Chun-Hung LIU, Zhi-Ting YE, Cheng-Teng YE, Po-Chang CHEN, Sheng-Che CHIOU
  • Patent number: 8264081
    Abstract: A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film comprises a Tantalum Nitride layer on a substrate, with a Titanium Nitride layer deposited thereon. The thickness of the entire multi-layer film may be approximately fifty Angstroms. The film has superior film characteristics, such as anti-diffusion capability, low resistivity, high density, and step coverage, when compared to films deposited by conventional chemical vapor deposition (CVD). The multi-layered barrier metal thin film of the present invention has improved adhesion characteristics and is particularly suited for metallization of a Copper film thereon.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: September 11, 2012
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Wei Pan, Yoshi Ono, David R. Evans, Sheng Teng Hsu
  • Patent number: 8242482
    Abstract: An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top electrode. The Si phosphor layer is interposed between the bottom and top electrodes. The nanotips may have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. Typically, the nanotips are formed from iridium oxide (IrOx) nanotips. A MOCVD process forms the Ir bottom electrode. The IrOx nanotips are grown from the Ir. In one aspect, the Si phosphor layer is a SRSO layer. In response to an SRSO annealing step, nanocrystalline SRSO is formed with nanocrystals having a size in the range of 1 to 10 nm.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: August 14, 2012
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Sheng Teng Hsu, Fengyan Zhang, Gregory M. Stecker, Robert A. Barrowcliff
  • Patent number: 8059178
    Abstract: A complementary metal oxide semiconductor (CMOS) imager flush reset circuit is provided. The flush reset circuit has an interface to receive first (e.g., VDD) and second (e.g., ground) reference voltages. The flush reset circuit has a solitary (flush) signal interface. There is also an interface connected to a transistor set power interface to supply a Vflush1 signal at least one threshold voltage different than the second reference voltage, in response to receiving a flush signal. The flush signal is used to create a CMOS imager hard reset prior to a soft reset.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: November 15, 2011
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Sheng Teng Hsu, Jong-Jan Lee
  • Patent number: 7968419
    Abstract: A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.
    Type: Grant
    Filed: September 21, 2008
    Date of Patent: June 28, 2011
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Tingkai Li, Sheng Teng Hsu, David R. Evans
  • Patent number: 7906825
    Abstract: A germanium (Ge) short wavelength infrared (SWIR) imager and associated fabrication process are provided. The imager comprises a silicon (Si) substrate with doped wells. An array of pin diodes is formed in a relaxed Ge-containing film overlying the Si substrate, each pin diode having a flip-chip interface. There is a Ge/Si interface, and a doped Ge-containing buffer interposed between the Ge-containing film and the Ge/Si interface. An array of Si CMOS readout circuits is bonded to the flip-chip interfaces. Each readout circuit has a zero volt diode bias interface.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: March 15, 2011
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Douglas J. Tweet, Jer-Shen Maa, Jong-Jan Lee, Sheng Teng Hsu
  • Patent number: 7905013
    Abstract: An iridium oxide (IrOx) nanowire neural sensor array and associated fabrication method are provided. The method provides a substrate with a conductive layer overlying the substrate, and a dielectric layer overlying the conductive layer. The substrate can be a material such as Si, SiO2, quartz, glass, or polyimide, and the conductive layer is a material such as ITO, SnO2, ZnO, TiO2, doped ITO, doped SnO2, doped ZnO, doped TiO2, TiN, TaN, Au, Pt, or Ir. The dielectric layer is selectively wet etched, forming contact holes with sloped walls in the dielectric layer and exposing regions of the conductive layer. IrOx nanowire neural interfaces are grown from the exposed regions of the conductive layer. The IrOx nanowire neural interfaces each have a cross-section in a range of 0.5 to 10 micrometers, and may be shaped as a circle, rectangle, or oval.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: March 15, 2011
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Fengyan Zhang, Bruce D. Ulrich, Wei Gao, Sheng Teng Hsu
  • Patent number: 7816753
    Abstract: An optical device with an iridium oxide (IrOx) electrode neural interface, and a corresponding fabrication method are provided. The method provides a substrate and forms a first conductive electrode overlying the substrate. A photovoltaic device having a first electrical interface is connected to the first electrode. A second electrical interface of the photovoltaic device is connected to a second conductive electrode formed overlying the photovoltaic device. An array of neural interface single-crystal IrOx nanostructures are formed overlying the second electrode, where x?4. The IrOx nanostructures can be partially coated with an electrical insulator, such as SiO2, SiN, TiO2, or spin on glass (SOG), leaving the IrOx distal ends exposed. In one aspect, a buffer layer is formed overlying the second electrode surface, made from a material such as LiNbO3, LiTaO3, or SA, for the purpose of orienting the growth direction of the IrOx nanostructures.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: October 19, 2010
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Fengyan Zhang, Sheng Teng Hsu
  • Patent number: 7811837
    Abstract: A method of fabricating an electroluminescent device includes, on a prepared substrate, depositing a rare earth-doped silicon-rich layer on gate oxide layer as a light emitting layer; and annealing and oxidizing the structure to repair any damage caused to the rare earth-doped silicon-rich layer; and incorporating the electroluminescent device into a CMOS IC. An electroluminescent device fabricated according to the method of the invention includes a substrate, a rare earth-doped silicon-rich layer formed on the gate oxide layer for emitting a light of a pre-determined wavelength; a top electrode formed on the rare earth-doped silicon-rich layer; and associated CMOS IC structures fabricated thereabout.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: October 12, 2010
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Tingkai Li, Wei Gao, Yoshi Ono, Sheng Teng Hsu
  • Patent number: 7811913
    Abstract: A method of fabricating a low, dark-current germanium-on-silicon PIN photo detector includes preparing a P-type silicon wafer; implanting the P-type silicon wafer with boron ions; activating the boron ions to form a P+ region on the silicon wafer; forming a boron-doped germanium layer on the P+ silicon surface; depositing an intrinsic germanium layer on the boron-doped germanium layer; cyclic annealing, including a relatively high temperature first anneal step and a relatively low temperature second anneal step; repeating the first and second anneal steps for about twenty cycles, thereby forcing crystal defects to the P+ germanium layer; implanting ions in the surface of germanium layer to form an N+ germanium surface layer and a PIN diode; activating the N+ germanium surface layer by thermal anneal; and completing device according to known techniques to form a low dark-current germanium-on-silicon PIN photodetector.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: October 12, 2010
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Jong-Jan Lee, Douglas J. Tweet, Jer-Shen Maa, Sheng Teng Hsu
  • Patent number: 7800148
    Abstract: A CMOS active pixel sensor includes a silicon-on-insulator substrate having a silicon substrate with an insulator layer formed thereon and a top silicon layer formed on the insulator layer. A stacked pixel sensor cell includes a bottom photodiode fabricated on the silicon substrate, for sensing light of a longest wavelength; a middle photodiode fabricated on the silicon substrate, for sensing light of a medium wavelength, which is stacked above the bottom photodiode; and a top photodiode fabricated on the top silicon layer, for sensing light of a shorter wavelength, which is stacked above the middle and bottom photodiodes. Pixel transistor sets are fabricated on the top silicon layer and are associated with each pixel sensor cell by electrical connections which extend between each of the photodiodes and respective pixel transistor(s). CMOS control circuitry is fabricated adjacent to an array of active pixel sensor cells and electrically connected thereto.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: September 21, 2010
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Jong-Jan Lee, Sheng Teng Hsu, Douglas James Tweet, Jer-Shen Maa
  • Patent number: 7786469
    Abstract: A silicon/germanium (SiGe) superlattice thermal sensor is provided with a corresponding fabrication method. The method forms an active CMOS device in a first Si substrate, and a SiGe superlattice structure on a second Si-on-insulator (SOI) substrate. The first substrate is bonded to the second substrate, forming a bonded substrate. An electrical connection is formed between the SiGe superlattice structure and the CMOS device, and a cavity is formed between the SiGe superlattice structure and the bonded substrate.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: August 31, 2010
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Jer-Shen Maa, Jinke Tang, Jong-Jan Lee, Douglas J. Tweet, Sheng Teng Hsu
  • Patent number: 7759756
    Abstract: A dual-pixel full color complementary metal oxide semiconductor (CMOS) imager is provided, along with an associated fabrication process. Two stand-alone pixels are used for three-color detection. The first pixel is a single photodiode, and the second pixel has two photodiodes built in a stacked structure. The two photodiode stack includes an n doped substrate, a bottom photodiode, and a top photodiode. The bottom photodiode has a bottom p doped layer overlying the substrate and a bottom n doped layer cathode overlying the bottom p doped layer. The top photodiode has a top p doped layer overlying the bottom n doped layer and a top n doped layer cathode overlying the top p doped layer. The single photodiode includes the n doped substrate, a p doped layer overlying the substrate, and an n doped layer cathode overlying the p doped layer.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: July 20, 2010
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Jong-Jan Lee, Sakae Wada, Sheng Teng Hsu
  • Patent number: 7759150
    Abstract: A nanorod sensor with a single plane of horizontally-aligned electrodes and an associated fabrication method are provided. The method provides a substrate and forms an intermediate electrode overlying a center region of the substrate. The intermediate electrode is a patterned bottom noble metal/Pt/Ti multilayered stack. TiO2 nanorods are formed over the substrate and intermediate electrode, and a TiO2 film may be formed overlying the TiO2 nanorods. The TiO2 nanorods and TiO2 film are formed in-situ, in the same process, by varying the substrate temperature. In other aspects, the TiO2 film is formed between the nanorods and the intermediate electrode. In yet another aspect, the TiO2 film is formed both above and below the nanorods. A single plane of top electrodes is formed overlying the TiO2 film from a top noble metal/Pt/Ti multilayered stack overlying the TiO2 film, which has been selectively etched to form separate top electrodes.
    Type: Grant
    Filed: May 22, 2007
    Date of Patent: July 20, 2010
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Fengyan Zhang, Bruce D. Ulrich, Wei Pan, Lawrence J. Charneski, Sheng Teng Hsu
  • Patent number: 7737391
    Abstract: A double-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cell is provided. The imager cell is fabricated from a silicon-on-insulator (SOI) substrate including a silicon (Si) substrate, a silicon dioxide insulator overlying the substrate, and a Si top layer overlying the insulator. A photodiode set is formed in the SOI substrate, including a first and second photodiode formed as a double-junction structure in the Si substrate. A third photodiode is formed in the Si top layer. A (imager sensing) transistor set is formed in the top Si layer. The transistor set is connected to the photodiode set and detects an independent output signal for each photodiode. The transistor set may be an eight-transistor (8T), a nine-transistor (9T), or an eleven-transistor (11T) cell.
    Type: Grant
    Filed: May 22, 2007
    Date of Patent: June 15, 2010
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Sheng Teng Hsu, Jong-Jan Lee
  • Patent number: 7727897
    Abstract: A method of etching a top electrode/ferroelectric stack using an etch stop layer includes forming a first layer of a first dielectric material on a substrate; forming a bottom electrode in the first layer of a first dielectric material; depositing an etch stop layer on the first layer of the first dielectric material and the bottom electrode, including forming a hole therein; depositing a layer of ferroelectric material and depositing top electrode material on the ferroelectric material to form a top electrode/ferroelectric stack; stack etching the top electrode and ferroelectric material; depositing a layer of a second dielectric material encapsulating the top electrode and ferroelectric material; etching the layer of the second dielectric material to form a sidewall about the top electrode and ferroelectric material; and depositing a second and third layers of the first dielectric material.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: June 1, 2010
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Bruce D. Ulrich, Lisa H. Stecker, Fengyan Zhang, Sheng Teng Hsu
  • Patent number: RE47382
    Abstract: A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: May 7, 2019
    Assignee: Xenogenic Development Limited Liability Company
    Inventors: Tingkai Li, Sheng Teng Hsu, David R. Evans