Abstract: A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.

Abstract: An optical device with an iridium oxide (IrOx) electrode neural interface, and a corresponding fabrication method are provided. The method provides a substrate and forms a first conductive electrode overlying the substrate. A photovoltaic device having a first electrical interface is connected to the first electrode. A second electrical interface of the photovoltaic device is connected to a second conductive electrode formed overlying the photovoltaic device. An array of neural interface single-crystal IrOx nanostructures are formed overlying the second electrode, where x?4. The IrOx nanostructures can be partially coated with an electrical insulator, such as SiO2, SiN, TiO2, or spin on glass (SOG), leaving the IrOx distal ends exposed. In one aspect, a buffer layer is formed overlying the second electrode surface, made from a material such as LiNbO3, LiTaO3, or SA, for the purpose of orienting the growth direction of the IrOx nanostructures.

Abstract: An iridium oxide (IrOx) nanowire protein sensor and associated fabrication method are presented. The method provides a substrate and forms overlying working and counter electrodes. A dielectric layer is deposited over the working and counter electrodes and contact holes are formed in the dielectric layer, exposing regions of the working and counter electrodes. IrOx nanowires (where 0?X?2) are grown from exposed regions of the working electrode. In one aspect, the IrOx nanowires are additionally grown on the dielectric, and subsequently etched from the dielectric. In another aspect, IrOx nanowires are grown from exposed regions of the counter electrode.

Abstract: An optical device with an iridium oxide (IrOx) electrode neural interface, and a corresponding fabrication method are provided. The method provides a substrate and forms a first conductive electrode overlying the substrate. A photovoltaic device having a first electrical interface is connected to the first electrode. A second electrical interface of the photovoltaic device is connected to a second conductive electrode formed overlying the photovoltaic device. An array of neural interface single-crystal IrOx nanostructures are formed overlying the second electrode, where x?4. The IrOx nanostructures can be partially coated with an electrical insulator, such as SiO2, SiN, TiO2, or spin on glass (SOG), leaving the IrOx distal ends exposed. In one aspect, a buffer layer is formed overlying the second electrode surface, made from a material such as LiNbO3, LiTaO3, or SA, for the purpose of orienting the growth direction of the IrOx nanostructures.

Abstract: A thermal expansion interface between silicon (Si) and gallium nitride (GaN) films using multiple buffer layers of aluminum compounds has been provided, along with an associated fabrication method. The method provides a (111) Si substrate and deposits a first layer of AlN overlying the substrate by heating the substrate to a relatively high temperature of 1000 to 1200° C. A second layer of AlN is deposited overlying the first layer of AlN at a lower temperature of 500 to 800° C. A third layer of AlN is deposited overlying the second layer of AlN by heating the substrate to the higher temperature range. Then, a grading Al1-XGaXN layer is formed overlying the third layer of AlN, where 0<X<1, followed by a fixed composition Al1-XGaXN layer overlying the first grading Al1-XGaXN layer. An epitaxial GaN layer can then be grown overlying the fixed composition Al1-XGaXN layer.

Abstract: A method is provided for forming a ZnO Si N—I—N EL device. The method comprises: forming an n-doped Si layer; forming a Si oxide (SiO2) layer overlying the n-doped Si layer; forming an n-type ZnO layer overlying the SiO2 layer; and, forming an electrode overlying the ZnO layer. The electrode can be a transparent material such as indium tin oxide, zinc oxyfluoride, or a conductive plastic. The n-doped Si layer can be polycrystalline or single-crystal Si. In some aspects, the Si oxide layer has a thickness in the range of 1 to 20 nm. More preferably, the thickness is 2 to 5 nm. The ZnO layer thickness is in the range of 10 to 200 nm.

Abstract: A triple-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cell is provided. The imager cell is made from a bulk silicon (Si) substrate. A photodiode set including a first, second, and third photodiode are formed as a triple-junction structure in the Si substrate. A transistor set is connected to the photodiode set, and detects an independent output signal for each photodiode. Typically, the transistor set is formed in the top surface of the substrate. For example, the Si substrate may be a p-doped Si substrate, and the photodiode triple-junction structure includes the first photodiode forming a pn junction from an n+-doped region at the Si substrate top surface, to an underlying p-doped region. The second photodiode forms a pn junction from the p-doped region to an underlying n-well, and the third photodiode forms a pn junction from the n-well to the underlying p-doped Si substrate.

Abstract: A method of making CMOS devices on strained silicon on glass includes preparing a glass substrate, including forming a strained silicon layer on the glass substrate; forming a silicon oxide layer by plasma oxidation of the strained silicon layer; depositing a layer of doped polysilicon on the silicon oxide layer; forming a polysilicon gate; implanting ions to form a LDD structure; depositing and forming a spacer dielectric on the gate structure; implanting and activation ions to form source and drain structures; depositing a layer of metal film; annealing the layer of metal film to form salicide on the source, drain and gate structures; removing any unreacted metal film; depositing a layer of interlayer dielectric; and forming contact holes and metallizing.

Abstract: A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate with a first thermal expansion coefficient (TEC), and forms a silicon-germanium (SiGe) film overlying the Si substrate. A buffer layer is deposited overlying the SiGe film. The buffer layer may be aluminum nitride (AlN) or aluminum-gallium nitride (AlGaN). A GaN film is deposited overlying the buffer layer having a second TEC, greater than the first TEC. The SiGe film has a third TEC, with a value in between the first and second TECs. In one aspect, a graded SiGe film may be formed having a Ge content ratio in a range of about 0% to 50%, where the Ge content increases with the graded SiGe film thickness.

Abstract: A silicon (Si)-on-insulator (SOI) high voltage transistor is provided with an associated fabrication process. The method provides a SOI substrate with a Si top layer. A control channel and an adjacent auxiliary channel are formed in the Si top layer. A control gate overlies the control channel and an auxiliary gate overlies the auxiliary channel. A source region is formed adjacent the control channel, and a lightly doped drain (LDD) region is interposed between the auxiliary channel and the drain. An interior drain region is interposed between the control and auxiliary channels. Typically, the Si top layer has a thickness in the range of 20 to 1000 nm. In one aspect, the Si top layer in the source, control channel, interior drain, and auxiliary channel regions is thinned to a thickness in the range of 5 to 200 nm, and raised source, drain, LDD, and interior drain regions are formed.

Abstract: A CMOS active pixel sensor includes a silicon-on-insulator substrate having a silicon substrate with an insulator layer formed thereon and a top silicon layer formed on the insulator layer. A stacked pixel sensor cell includes a bottom photodiode fabricated on the silicon substrate, for sensing light of a longest wavelength; a middle photodiode fabricated on the silicon substrate, for sensing light of a medium wavelength, which is stacked above the bottom photodiode; and a top photodiode fabricated on the top silicon layer, for sensing light of a shorter wavelength, which is stacked above the middle and bottom photodiodes. Pixel transistor sets are fabricated on the top silicon layer and are associated with each pixel sensor cell by electrical connections which extend between each of the photodiodes and respective pixel transistor(s). CMOS control circuitry is fabricated adjacent to an array of active pixel sensor cells and electrically connected thereto.

Abstract: A ZnO asperity-covered carbon nanotube (CNT) device has been provided, along with a corresponding fabrication method. The method comprises: forming a substrate; growing CNTs from the substrate; conformally coating the CNTs with ZnO; annealing the ZnO-coated CNTs; and, forming ZnO asperities on the surface of the CNTs in response to the annealing. In one aspect, the ZnO asperities have a density in the range of about 100 to 1000 ZnO asperities per CNT. The density is dependent upon the deposited ZnO film thickness and annealing parameters. The CNTs are conformally coating with ZnO using a sputtering, chemical vapor deposition (CVD), spin-on, or atomic layer deposition (ALD). For example, an ALD process can be to deposit a layer of ZnO over the CNTs having a thickness in the range of 1.2 to 200 nanometers (nm).

Abstract: A multilayer thermal expansion interface between silicon (Si) and gallium nitride (GaN) films is provided, along with an associated fabrication method. The method provides a (111) Si substrate and forms a first layer of a first film overlying the substrate. The Si substrate is heated to a temperature in the range of about 300 to 800° C., and the first layer of a second film is formed in compression overlying the first layer of the first film. Using a lateral nanoheteroepitaxy overgrowth (LNEO) process, a first GaN layer is grown overlying the first layer of second film. Then, the above-mentioned processes are repeated: forming a second layer of first film; heating the substrate to a temperature in the range of about 300 to 800° C.; forming a second layer of second film in compression; and, growing a second GaN layer using the LNEO process.

Abstract: A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate that is heated to a temperature in a range of about 300 to 800° C., and a first film is formed in compression overlying the Si substrate. The first film material may be InP, SiGe, GaP, GaAs, AlN, AlGaN, an AlN/graded AlGaN (Al1?xGaxN (0<x<1)) stack, or a AlN/graded AlGaN/GaN stack. The first film is then nanoscale patterned and a lateral nanoheteroepitaxy overgrowth (LNEO) process is used to grow a first GaN layer. The above-mentioned processes are repeated, forming a second film in compression that is nanoscale patterned, and a second GaN layer is grown using the LNEO process. The first and second GaN layers are formed by heating the Si substrate to a temperature in a range of 1000 to 1200° C.

Abstract: An iridium oxide (IrOx) nanowire neural sensor array and associated fabrication method are provided. The method provides a substrate with a conductive layer overlying the substrate, and a dielectric layer overlying the conductive layer. The substrate can be a material such as Si, SiO2, quartz, glass, or polyimide, and the conductive layer is a material such as ITO, SnO2, ZnO, TiO2, doped ITO, doped SnO2, doped ZnO, doped TiO2, TiN, TaN, Au, Pt, or Ir. The dielectric layer is selectively wet etched, forming contact holes with sloped walls in the dielectric layer and exposing regions of the conductive layer. IrOx nanowire neural interfaces are grown from the exposed regions of the conductive layer. The IrOx nanowire neural interfaces each have a cross-section in a range of 0.5 to 10 micrometers, and may be shaped as a circle, rectangle, or oval.

Abstract: A method of fabricating a silicon-on-plastic layer via layer transfer includes depositing a layer of SiGe on a silicon substrate; depositing a layer of silicon; implanting splitting hydrogen ions into the silicon substrate; bonding a glass substrate to the silicon layer; splitting the wafer; removing the silicon layer and a portion of the SiGe layer; depositing a dielectric on the silicon side of the silicon-on-glass wafer; applying adhesive and bonding a plastic substrate to the silicon side of the silicon-on-glass wafer; removing the glass from the glass side of the bonded, silicon-on-glass wafer to form a silicon-on-plastic wafer; and completing a desired IC device on the silicon-on-plastic. Multi-level structure may be fabricated according to the method of the invention by repeating the last few steps of the method of the invention.

Abstract: A nanorod sensor with a single plane of horizontally-aligned electrodes and an associated fabrication method are provided. The method provides a substrate and forms an intermediate electrode overlying a center region of the substrate. The intermediate electrode is a patterned bottom noble metal/Pt/Ti multilayered stack. TiO2 nanorods are formed over the substrate and intermediate electrode, and a TiO2 film may be formed overlying the TiO2 nanorods. The TiO2 nanorods and TiO2 film are formed in-situ, in the same process, by varying the substrate temperature. In other aspects, the TiO2 film is formed between the nanorods and the intermediate electrode. In yet another aspect, the TiO2 film is formed both above and below the nanorods. A single plane of top electrodes is formed overlying the TiO2 film from a top noble metal/Pt/Ti multilayered stack overlying the TiO2 film, which has been selectively etched to form separate top electrodes.

Abstract: A method is provided for fabricating a silicon (Si)-on-insulator (SOI) double-diffused metal oxide semiconductor transistor (DMOST) with a stepped channel thickness. The method provides a SOI substrate with a Si top layer having a surface. A thinned area of the Si top layer is formed, and a source region is formed in the thinned Si top layer area. The drain region is formed in an un-thinned area of the Si top layer. The channel has a first thickness adjacent the source region with first-type dopant, and a second thickness, greater than the first thickness, adjacent the drain region. The channel also has a sloped thickness between the first and second thicknesses. The second and sloped thicknesses have a second-type dopant, opposite of the first-type dopant. A stepped gate overlies the channel.

Abstract: A nanowire sensor with a self-aligned top electrode support insulator, and associated fabrication process are provided. The method begins with a doped silicon-containing substrate. A growth-promotion metal is deposited overlying the substrate. A silicon nitride electrode support is formed overlying the growth-promotion metal. Nanowires are grown from exposed regions of the growth-promotion metal and an insulator is deposited over the nanowires. A top insulator layer is removed to expose tips of the nanowires, and a top electrode metal is deposited overlying the nanowire tips and silicon nitride electrode support. Next, a stack etch is selectively performed, etching down to the level of the growth-promotion metal. A top electrode island is left that is centered on the silicon nitride electrode support and connected to the growth-promotion metal via the nanowires. Then, the sensor is dipped in a buffered hydrofluoric (BHF) solution, to remove any remaining insulator and to expose the nanowires.

Abstract: A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate and forms a first aluminum (Al)-containing film in compression overlying the Si substrate. Nano-column holes are formed in the first Al-containing film, which exposes regions of the underlying Si substrate. A layer of GaN layer is selectively grown from the exposed regions, covering the first Al-containing film. The GaN is grown using a lateral nanoheteroepitaxy overgrowth (LNEO) process. The above-mentioned processes are reiterated, forming a second Al-containing film in compression, forming nano-column holes in the second Al-containing film, and selectively growing a second GaN layer. Film materials such as Al2O3, Si1-xGex, InP, GaP, GaAs, AlN, AlGaN, or GaN, may be initially grown at a low temperature. By increasing the growth temperatures, a compressed layer of epitaxial GaN can be formed on a Si substrate.