Patents by Inventor Sheng-Tsai Wu

Sheng-Tsai Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11004816
    Abstract: A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: May 11, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Ang-Ying Lin, Sheng-Tsai Wu, Tao-Chih Chang, Wei-Chung Lo
  • Publication number: 20210118860
    Abstract: An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip.
    Type: Application
    Filed: May 27, 2020
    Publication date: April 22, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Sheng-Tsai Wu, Yu-Min Lin, Yuan-Yin Lo, Ang-Ying Lin, Tzu-Hsuan Ni, Chao-Jung Chen, Shin-Yi Huang
  • Publication number: 20210111126
    Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a wiring structure and an interposer via electrically connected to the wiring structure; a plurality of semiconductor chips located on a first surface of the interposer and electrically connected to each other through the interposer; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface, wherein the plurality of semiconductor chips are electrically connected to the redistribution circuit structure through at least the interposer.
    Type: Application
    Filed: October 8, 2020
    Publication date: April 15, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Ang-Ying Lin, Yu-Min Lin, Shin-Yi Huang, Sheng-Tsai Wu, Yuan-Yin Lo, Tzu-Hsuan Ni, Chao-Jung Chen
  • Publication number: 20210111125
    Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, a through via penetrating through the dielectric body, and a wiring structure located in each of the plurality of semiconductor bodies; a plurality of semiconductor chips located side by side on a first surface of the interposer and electrically connected to the wiring structure; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface of the interposer and electrically connected to the plurality of semiconductor chips through the through via.
    Type: Application
    Filed: August 27, 2020
    Publication date: April 15, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Chao-Jung Chen, Yu-Min Lin, Sheng-Tsai Wu, Shin-Yi Huang, Ang-Ying Lin, Tzu-Hsuan Ni, Yuan-Yin Lo
  • Publication number: 20210111153
    Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.
    Type: Application
    Filed: October 8, 2020
    Publication date: April 15, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Ang-Ying Lin, Sheng-Tsai Wu, Chao-Jung Chen, Tzu-Hsuan Ni, Shin-Yi Huang, Yuan-Yin Lo
  • Publication number: 20210082810
    Abstract: A package substrate includes a substrate, an insulating protective layer and an interposer. The substrate has a first surface and a second surface opposing to the first surface. The substrate includes a plurality of first conductive pads embedded in the first surface. The insulating protective layer is disposed on the first surface of the substrate. The insulating protective layer has an opening for exposing the first conductive pads embedded in the first surface of the substrate. The interposer has a top surface and a bottom surface opposing to the top surface. The interposer includes a plurality of conductive vias and a plurality of second conductive pads located on the bottom surface. The interposer is located in a recess defined by the opening of the insulating protective layer and the first surface of the substrate. Each of the second conductive pads is electrically connected to corresponding first conductive pad.
    Type: Application
    Filed: November 12, 2020
    Publication date: March 18, 2021
    Applicants: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Tao-Chih Chang, Yu-Min Lin, Sheng-Tsai Wu
  • Publication number: 20200075519
    Abstract: A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 5, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Ang-Ying Lin, Sheng-Tsai Wu, Tao-Chih Chang, Wei-Chung Lo
  • Patent number: 10540474
    Abstract: A chip temperature computation method and a chip temperature computation device are provided. The chip temperature computation method includes: computing an upper layer thermal resistance and a lower layer thermal resistance of a chip, computing a total thermal resistance of the chip, and computing a temperature of the chip according to the total thermal resistance.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: January 21, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Heng-Chieh Chien, Sheng-Tsai Wu, Ming-Ji Dai, Chih-Ming Shen
  • Patent number: 10390390
    Abstract: An electronic apparatus and a light-emitting module driving circuit thereof are provided. The electronic apparatus includes a light-emitting module and a driving circuit. The driving circuit is coupled to the light-emitting module and is configured to generate a driving signal set to drive the light-emitting module. The driving circuit includes a first driver, a second driver, and a switching circuit. The first driver receives a control signal related to an operation status of the electronic apparatus and generates a first signal set according to the control signal. The second driver includes at least one resistor which receives system power and accordingly generates a second signal set. The switching circuit is coupled to the first driver and the second driver to receive the first signal set and the second signal set, respectively. When the switching circuit does not receive the first signal set, the switching circuit takes the second signal set as the driving signal set.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 20, 2019
    Assignee: PEGATRON CORPORATION
    Inventors: Sheng-Tsai Wu, Chun-Hsien Chen, Yi-Chun Chou
  • Publication number: 20190188357
    Abstract: A chip temperature computation method and a chip temperature computation device are provided. The chip temperature computation method includes: computing an upper layer thermal resistance and a lower layer thermal resistance of a chip, computing a total thermal resistance of the chip, and computing a temperature of the chip according to the total thermal resistance.
    Type: Application
    Filed: March 15, 2018
    Publication date: June 20, 2019
    Applicant: Industrial Technology Research Institute
    Inventors: Heng-Chieh Chien, Sheng-Tsai Wu, Ming-Ji Dai, Chih-Ming Shen
  • Publication number: 20190191503
    Abstract: An electronic apparatus and a light-emitting module driving circuit thereof are provided. The electronic apparatus includes a light-emitting module and a driving circuit. The driving circuit is coupled to the light-emitting module and is configured to generate a driving signal set to drive the light-emitting module. The driving circuit includes a first driver, a second driver, and a switching circuit. The first driver receives a control signal related to an operation status of the electronic apparatus and generates a first signal set according to the control signal. The second driver includes at least one resistor which receives system power and accordingly generates a second signal set. The switching circuit is coupled to the first driver and the second driver to receive the first signal set and the second signal set, respectively. When the switching circuit does not receive the first signal set, the switching circuit takes the second signal set as the driving signal set.
    Type: Application
    Filed: November 28, 2018
    Publication date: June 20, 2019
    Applicant: PEGATRON CORPORATION
    Inventors: Sheng-Tsai Wu, Chun-Hsien Chen, Yi-Chun Chou
  • Patent number: 9448121
    Abstract: A measurement method, a measurement apparatus, and a computer program product for measuring a thermoelectric module are provided. A temperature is provided to the thermoelectric module. A current is applied to the thermoelectric module to turn both sides of the thermoelectric module into a hot side and a cold side. The temperature of the hot side is higher than that of the cold side. A terminal voltage of the thermoelectric module, a hot side temperature of the hot side, and a cold side temperature of the cold side are measured at different time points. A thermoelectric relationship between the terminal voltages and differences between the hot side temperatures and the corresponding cold side temperatures is obtained according to the terminal voltages, the hot side temperatures, and the cold side temperatures. At least one first parameter of the thermoelectric module is estimated according to the thermoelectric relationship.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: September 20, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Heng-Chieh Chien, Ming-Ji Dai, Sheng-Tsai Wu, Huey-Lin Hsieh, Jing-Yi Huang
  • Patent number: 9252054
    Abstract: A thinned integrated circuit device and manufacturing process for the same are disclosed. The manufacturing process includes forming a through-silicon via (TSV) on a substrate, a first terminal of the TSV is exposed on a first surface of the substrate, disposing a bump on the first surface of the substrate to make the bump electrically connected with the TSV, disposing an integrated circuit chip (IC) on the bump so that a first side of the IC is connected to the bump, disposing a thermal interface material (TIM) layer on a second side of the IC opposite to the first side of the IC, attaching a heat-spreader cap on the IC by the TIM layer, and backgrinding a second surface of the substrate to expose the TSV to the second surface of the substrate while carrying the heat-spreader cap.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: February 2, 2016
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Sheng-Tsai Wu, Heng-Chieh Chien, John H. Lau, Yu-Lin Chao, Wei-Chung Lo
  • Publication number: 20150076682
    Abstract: A thinned integrated circuit device and manufacturing process for the same are disclosed. The manufacturing process includes forming a through-silicon via (TSV) on a substrate, a first terminal of the TSV is exposed on a first surface of the substrate, disposing a bump on the first surface of the substrate to make the bump electrically connected with the TSV, disposing an integrated circuit chip (IC) on the bump so that a first side of the IC is connected to the bump, disposing a thermal interface material (TIM) layer on a second side of the IC opposite to the first side of the IC, attaching a heat-spreader cap on the IC by the TIM layer, and backgrinding a second surface of the substrate to expose the TSV to the second surface of the substrate while carrying the heat-spreader cap.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 19, 2015
    Inventors: Sheng-Tsai WU, Heng-Chieh CHIEN, John H. LAU, Yu-Lin CHAO, Wei-Chung LO
  • Publication number: 20130276464
    Abstract: A measurement method, a measurement apparatus, and a computer program product for measuring a thermoelectric module are provided. A temperature is provided to the thermoelectric module. A current is applied to the thermoelectric module to turn both sides of the thermoelectric module into a hot side and a cold side. The temperature of the hot side is higher than that of the cold side. A terminal voltage of the thermoelectric module, a hot side temperature of the hot side, and a cold side temperature of the cold side are measured at different time points. A thermoelectric relationship between the terminal voltages and differences between the hot side temperatures and the corresponding cold side temperatures is obtained according to the terminal voltages, the hot side temperatures, and the cold side temperatures. At least one first parameter of the thermoelectric module is estimated according to the thermoelectric relationship.
    Type: Application
    Filed: April 1, 2013
    Publication date: October 24, 2013
    Inventors: Heng-Chieh Chien, Ming-Ji Dai, Sheng-Tsai Wu, Huey-Lin Hsieh, Jing-Yi Huang
  • Publication number: 20130234325
    Abstract: By adding particles of high thermal conductivity and low thermal expansion coefficient into the copper as a composite material and filling with the composite material into the through-via hole, the mismatch of the coefficient of thermal expansion and the stress of the through-silicon via are lowered and the thermal conductivity of the through-silicon via is increased.
    Type: Application
    Filed: April 30, 2013
    Publication date: September 12, 2013
    Applicant: Industrial Technology Research Institute
    Inventors: Ming-Ji Dai, Ra-Min Tain, Chun-Hsien Chien, Heng-Chieh Chien, Sheng-Tsai Wu
  • Patent number: 8519524
    Abstract: A chip stacking structure including a carrier, a first redistribution layer, a second redistribution layer, at least one first chip, at least one second chip, and at least one conductor is provided. The carrier has a first surface and a second surface opposite to each other. The carrier has at least one through hole. The first and second redistribution layers are disposed on the first and second surfaces of the carrier, respectively. The first and second chips are disposed on the first and second surfaces of the carrier and electrically connected with the first and second redistribution layers, respectively. The conductor is disposed on one of the first and second chips. The conductor is disposed in the through hole. The first and second chips are electrically connected by the conductor. A gap is formed between the conductor and an inner wall of the carrier which surrounds the through hole.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: August 27, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Sheng-Tsai Wu, John H. Lau, Heng-Chieh Chien, Ra-Min Tain, Ming-Ji Dai, Yu-Lin Chao