Patents by Inventor Sheng-Wei Lee

Sheng-Wei Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160145737
    Abstract: An ion implantation method includes generating a first ion beam and a second ion beam, the first ion beam having a different configuration from the second ion beam. The method further includes scanning and directing the first ion beam along a first path toward a workpiece to perform ion implantation on the workpiece. The method alternatively includes directing the second ion beam along a second path toward the workpiece to perform ion implantation on the workpiece. The first path is different from the second path.
    Type: Application
    Filed: January 29, 2016
    Publication date: May 26, 2016
    Inventors: Shao-Hua WANG, Ming-Te CHEN, Sheng-Wei LEE
  • Patent number: 9267982
    Abstract: A processing apparatus includes an end station configured to support thereon a workpiece, an ion beam generator and a scanning device. The ion beam generator is configured to generate an ion beam toward the end station. The scanning device is configured to scan the ion beam in a transverse scanning direction. The scanning device is configured to be disposed in a first path of the ion beam toward the end station and out of a second path of the ion beam toward the end station.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: February 23, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Hua Wang, Ming-Te Chen, Sheng-Wei Lee
  • Publication number: 20150357548
    Abstract: A method for forming a thermoelectric film having a micro groove includes the following steps: A) forming a plurality of parallel sacrificing wires by electrospinning, a diameter of each sacrificing wire being 100-500 nm; B) coating a thermoelectric film having a thickness of 80-200 nm on a part of a surface of each sacrificing wire; and C) removing the sacrificing wires from the thermoelectric films and thus obtaining the thermoelectric films each having the micro groove, a radio side of each thermoelectric film being open to the surroundings. The thermoelectric films finally prepared can have higher size uniformity without the disadvantage of catalyst residual. Further, the thermoelectric films each have a size smaller than the mean free path of phonons in one dimension, and thus the thermoelectric properties of the thermoelectric films can be improved.
    Type: Application
    Filed: July 17, 2014
    Publication date: December 10, 2015
    Inventors: Sheng-Wei LEE, Yi-Fan NIU, Pei-Wen LI, Cheng-Lun HSIN, Chung-Jen TSENG
  • Publication number: 20150198556
    Abstract: The present invention relates to a sensing electrode of an enzyme-based sensor, and the enzyme-based sensor comprising the same can be stably stored at room temperature. The sensing electrode comprises: an electrode substrate and an enzyme sensing layer formed thereon, wherein the enzyme sensing layer comprises sequentially laminated layers of: a first carbon material-nano metal layer containing a carbon material and nano-metal particles; an ionic liquid layer comprising an ionic liquid consisting of a cation and an anion; a second carbon material-nano metal layer containing a carbon material and nano-metal particles; and an enzyme layer. The present invention also provides a method for manufacturing the sensing electrode of an enzyme-based sensor.
    Type: Application
    Filed: July 16, 2014
    Publication date: July 16, 2015
    Inventors: Jeng-Kuei CHANG, Jia-Wun WU, Sheng-Wei LEE, Chueh-Han WANG, Yi-Chen WANG
  • Publication number: 20150162166
    Abstract: A system, a method, and a non-transitory computer readable storage medium for controlling an ion implanter are disclosed herein. The system includes a sample module and a control module. The sample module is configured to generate a summarized value from process data of the ion implanter, and the process data correspond to a control parameter. The control module is configured to tune a control parameter, and the control module performs an ion implantation by releasing tools of the ion implanter in accordance with the control parameter when the summarized value meets a predetermined stability requirement.
    Type: Application
    Filed: December 6, 2013
    Publication date: June 11, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Feng TSAI, Chia-Tong HO, Chia-Hsing LlAO, Sheng-Wei LEE, Jo-Fei WANG, Jong-I MOU
  • Publication number: 20150162634
    Abstract: The preparation method of electrolytes provided by the present invention involves applications of a first solid oxide powder and a second solid oxide powder, both of which are prepared by using a sol-gel process and a calcination process. Each of the first and second solid oxide powders is a Perovskite-type oxide. After the first and second solid oxide powders are readily mixed, they are compressed into a pellet and then sintered to prepare the afore-mentioned electrolytes for SOFC. It is found in the present invention that by mixing and compressing different solid oxide powders, the solid oxide powder having smaller particle size can fill into the gaps of the other solid oxide powder. After the pellet is sintered, the density of the product is significantly improved.
    Type: Application
    Filed: February 13, 2015
    Publication date: June 11, 2015
    Inventors: Sheng-Wei LEE, Kan-Rong LEE, Jing-Chie LIN, Chuan LI, Chung-Jen TSENG, Jeng-Kuei CHANG, Shian-Ching JANG, I-Ming HUNG, Chi-Shiung HSI, Sheng-Long LEE, Yen-Jiun CHIANG, Yu-Shuo HUANG
  • Publication number: 20150037694
    Abstract: The preparation method of electrolytes provided by the present invention includes a first solid oxide powder and a second solid oxide powder, both of which are prepared by using a sol-gel process and a calcination process. Each of the first and second solid oxide powders is a Perovskite-type oxide. After the first and second solid oxide powders are readily mixed, they are compressed into a pellet and then sintered to prepare the afore-mentioned electrolytes for SOFC. It is found in the present invention that by mixing and compressing different solid oxide powders, the solid oxide powder having smaller particle size can fill into the gaps of the other solid oxide powder. After the pellet is sintered, the density of the product is significantly improved.
    Type: Application
    Filed: September 20, 2013
    Publication date: February 5, 2015
    Applicant: NATIONAL CENTRAL UNIVERSITY
    Inventors: SHENG-WEI LEE, KAN-RONG LEE, JING-CHIE LIN, CHUAN LI, CHUNG-JEN TSENG, JENG-KUEI CHANG, SHIANG-CHING JANG, I-MING HUNG, CHI-SHIUNG HSI, SHENG-LONG LEE, YEN-CHUN CHIANG
  • Publication number: 20140272178
    Abstract: An ion implantation apparatus and a method for ion implantation provides for implanting multiple substrates simultaneously. The different substrates are on corresponding platens within an ion implantation chamber or they may be positioned on separate substrate holders on a single oversized platen. The substrates and platen or platens, are translatable with respect to an ion beam, the individual substrates are rotatable and the position of the substrates relative to one another in the ion implantation chamber are movable. By rotating, translating and repositioning substrates during the ion implantation process, the entirety of all substrates are implanted by an ion beam even when the ion beam has a relatively small footprint and a relatively short scan length, compared to the diameters of the substrates undergoing implantation.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Hua WANG, Ming-Te Chen, Sheng-Wei Lee
  • Publication number: 20140227453
    Abstract: A processing apparatus includes an end station configured to support thereon a workpiece, an ion beam generator and a scanning device. The ion beam generator is configured to generate an ion beam toward the end station. The scanning device is configured to scan the ion beam in a transverse scanning direction. The scanning device is configured to be disposed in a first path of the ion beam toward the end station and out of a second path of the ion beam toward the end station.
    Type: Application
    Filed: February 11, 2013
    Publication date: August 14, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Hua WANG, Ming-Te CHEN, Sheng-Wei LEE
  • Patent number: 7498224
    Abstract: A method for growing strained Si layer and relaxed SiGe layer with multiple Ge quantum dots (QDs) on a substrate is disclosed. The method can reduce threading dislocation density, decrease surface roughness of the strained silicon and further shorten growth time for forming epitaxy layers than conventional method. The method includes steps of: providing a silicon substrate, forming a multiple Ge QDs layers; forming a layer of relaxed SixGe1-x; and forming a strained silicon layer in subsequence; wherein x is greater than 0 and less than 1.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: March 3, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Pang-Shiu Chen, Sheng-Wei Lee, Lih-Juann Chen, Chee-Wee Liu
  • Patent number: 7202512
    Abstract: A construction of thin strain-relaxed SiGe layers and method for fabricating the same is provided. The construction includes a semiconductor substrate, a SiGe buffer layer formed on the semiconductor substrate, a Si(C) layer formed on the SiGe buffer layer, and an relaxed SiGe epitaxial layer formed on the Si(C) layer. The Si(C) layer is employed to change the strain-relaxed mechanism of the relaxed SiGe epitaxial layer formed on the Si(C) layer. Therefore, a thin relaxed SiGe epitaxial layer with low threading dislocation density, smooth surface is available. The fabricating time for fabricating the strain-relaxed SiGe layers is greatly reduced and the surface roughness is also improved.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: April 10, 2007
    Assignee: Industrial Technology Research Institute
    Inventors: Pang-Shiu Chen, Sheng-Wei Lee, Kao-Feng Liao, Lih-Juann Chen, Chee-Wee Liu
  • Publication number: 20060255331
    Abstract: A method for growing strained Si layer and relaxed SiGe layer with multiple Ge quantum dots (QDs) on a substrate is disclosed. The method can reduce threading dislocation density, decrease surface roughness of the strained silicon and further shorten growth time for forming epitaxy layers than conventional method. The method includes steps of: providing a silicon substrate, forming a multiple Ge QDs layers; forming a layer of relaxed SixGe1-x; and forming a strained silicon layer in subsequence; wherein x is greater than 0 and less than 1.
    Type: Application
    Filed: July 20, 2006
    Publication date: November 16, 2006
    Applicant: Industrial Technology Research Institute
    Inventors: Pang-Shiu Chen, Sheng-Wei Lee, Lih-Juann Chen, Chee-Wee Liu
  • Patent number: 7102153
    Abstract: A method for growing strained Si layer and relaxed SiGe layer with multiple Ge quantum dots (QDs) on a substrate is disclosed. The method can reduce threading dislocation density, decrease surface roughness of the strained silicon and further shorten growth time for forming epitaxy layers than conventional method. The method includes steps of: providing a silicon substrate, forming a multiple Ge QDs layers; forming a layer of relaxed SixGe1-x; and forming a strained silicon layer in subsequence; wherein x is greater than 0 and less than 1.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: September 5, 2006
    Assignee: Industrial Technology Research Institute
    Inventors: Pang-Shiu Chen, Sheng-Wei Lee, Lih-Juann Chen, Chee-Wee Liu
  • Publication number: 20050179028
    Abstract: A construction of thin strain-relaxed SiGe layers and method for fabricating the same is provided. The construction includes a semiconductor substrate, a SiGe buffer layer formed on the semiconductor substrate, a Si(C) layer formed on the SiGe buffer layer, and an relaxed SiGe epitaxial layer formed on the Si(C) layer. The Si(C) layer is employed to change the strain-relaxed mechanism of the relaxed SiGe epitaxial layer formed on the Si(C) layer. Therefore, a thin relaxed SiGe epitaxial layer with low threading dislocation density, smooth surface is available. The fabricating time for fabricating the strain-relaxed SiGe layers is greatly reduced and the surface roughness is also improved.
    Type: Application
    Filed: August 11, 2004
    Publication date: August 18, 2005
    Inventors: Pang-Shiu Chen, Sheng-Wei Lee, Kao-Feng Liao, Lih-Juann Chen, Chee-Wee Liu
  • Publication number: 20050045870
    Abstract: A method for growing strained Si layer and relaxed SiGe layer with multiple Ge quantum dots (QDs) on a substrate is disclosed. The method can reduce threading dislocation density, decrease surface roughness of the strained silicon and further shorten growth time for forming epitaxy layers than conventional method. The method includes steps of: providing a silicon substrate, forming a multiple Ge QDs layers; forming a layer of relaxed SixGe1-x; and forming a strained silicon layer in subsequence; wherein x is greater than 0 and less than 1.
    Type: Application
    Filed: August 17, 2004
    Publication date: March 3, 2005
    Applicant: Industrial Technology Research Institute
    Inventors: Pang Chen, Sheng-Wei Lee, Lih-Juann Chen, Chee-Wee Liu