Patents by Inventor Sheng-Wei Wu

Sheng-Wei Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220300170
    Abstract: An electronic device includes a temporary memory, a non-volatile memory and a processor. The temporary memory includes at least one secure region. The non-volatile memory is configured to store at least one higher-level secure program and a plurality of commands. The processor is connected to the temporary memory and the non-volatile memory for executing the plurality of commands to: when receiving a wake-up command, initialize the at least one secure region; and through the at least one higher-level secure program, recover the at least one secure region, or decrypt encrypted data stored in the non-volatile memory to recover the at least one secure region. In addition, a hibernation recovery method is also disclosed herein.
    Type: Application
    Filed: October 21, 2021
    Publication date: September 22, 2022
    Inventors: Yu-Ting Ting, Sheng-Tzu Yang, Chang-Hao Wu, Chen-Wei Yu
  • Publication number: 20220285395
    Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain
    Type: Application
    Filed: May 28, 2021
    Publication date: September 8, 2022
    Inventors: Tsu Ching Yang, Feng-Cheng Yang, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, Hung-Chang Sun, Chen-Jun Wu, Chung-Te Lin
  • Publication number: 20220285384
    Abstract: A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.
    Type: Application
    Filed: March 3, 2021
    Publication date: September 8, 2022
    Inventors: Tsu Ching Yang, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, Hung-Chang Sun, Chen-Jun Wu, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20220275500
    Abstract: The present disclosure relates to exclusion rings for use in processing a semiconductor substrate in a processing chamber, such as a chemical vapor deposition chamber. The exclusion ring includes an alignment structure that cooperates with an alignment structure on a platen on which the exclusion ring will rest during processing of the wafer. The first alignment structure includes a guiding surface which promotes the reception of and positioning of the second alignment structure within the first alignment structure. Methods of utilizing the described exclusion rings are also described.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Inventors: Ming-Yi SHEN, Hsin-Lin WU, Yao-Fong DAI, Pei-Yuan TAI, Chin-Wei CHEN, Yin-Tun CHOU, Yuan-Hsin CHI, Sheng-Yuan LIN
  • Publication number: 20220278127
    Abstract: A semiconductor memory structure includes a ferroelectric layer and a channel layer formed over the ferroelectric layer. The structure also includes a source structure and a drain structure formed over the channel layer. The structure further includes a first isolation structure formed between the source structure and the drain structure. The source structure extends over the cap layer and towards the drain structure.
    Type: Application
    Filed: September 1, 2021
    Publication date: September 1, 2022
    Inventors: Hung-Chang Sun, Sheng-Chih Lai, Cheng-Jun Wu, Yu-Wei Jiang, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20220254791
    Abstract: The present disclosure relates to an integrated chip including a three-dimensional memory array. The three-dimensional memory array includes a first local line and a second local line that are elongated vertically, a first memory cell extending between the first local line and the second local line, and a second memory cell directly under the first memory cell, extending between the first local line and the second local line, and coupled in parallel with the first memory cell. The first memory cell is coupled to a first word line and the second memory cell is coupled to a second word line. The first word line and the second word line are elongated horizontally. A first global line is disposed at a first height and is elongated horizontally. A first selector extends vertically from the first local line to the first global line.
    Type: Application
    Filed: February 5, 2021
    Publication date: August 11, 2022
    Inventors: Cheng-Jun Wu, Yu-Wei Jiang, Sheng-Chih Lai
  • Patent number: 11402407
    Abstract: A positionable probe card includes a space transformer, a plurality of positioning pins, and a probe head. The space transformer includes a space transforming substrate, the space transforming substrate includes a plurality of apertures, and the positioning pins are respectively fixed in the apertures. The probe head includes a plurality of positioning holes, and the positioning pins are respectively inserted into corresponding positioning holes. In addition, a method of manufacturing a positionable probe card is also disclosed herein.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: August 2, 2022
    Assignee: MPI Corporation
    Inventors: Zhi-Wei Su, Tzung-Je Tzeng, Wen-Chi Chen, Huo-Kang Hsu, Hsueh-Chih Wu, Sheng-Wei Lin, Chin-Yi Lin, Che-Wei Lin, Jian-Kai Hong, Shu-Jui Chang
  • Publication number: 20220208581
    Abstract: The present disclosure relates to a contamination controlled semiconductor processing system. The contamination controlled semiconductor processing system includes a processing chamber, a contamination detection system, and a contamination removal system. The processing chamber is configured to process a wafer. The contamination detection system is configured to determine whether a contamination level on a surface of the door is greater than a baseline level. The contamination removal system is configured to remove contaminants from the surface of the door in response to the contamination level being greater than the baseline level.
    Type: Application
    Filed: March 21, 2022
    Publication date: June 30, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo Chen CHEN, Sheng-Wei Wu, Yung-Li Tsai
  • Patent number: 11282728
    Abstract: The present disclosure relates to a contamination controlled semiconductor processing system. The contamination controlled semiconductor processing system includes a processing chamber, a contamination detection system, and a contamination removal system. The processing chamber is configured to process a wafer. The contamination detection system is configured to determine whether a contamination level on a surface of the door is greater than a baseline level. The contamination removal system is configured to remove contaminants from the surface of the door in response to the contamination level being greater than the baseline level.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: March 22, 2022
    Inventors: Bo Chen Chen, Sheng-Wei Wu, Yung-Li Tsai
  • Publication number: 20210215424
    Abstract: The present disclosure is directed to a wafer drying system and method that detects airborne molecular contaminants in a drying gas as a feedback parameter for a single wafer or multi-wafer drying process. For example, the system comprises a wafer drying station configured to dispense a drying gas over one or more wafers to dry the one or more wafers, a valve configured to divert the drying gas to a first portion and a second portion, and an exhaust line configured to exhaust the first portion of the drying gas. The system further comprises a detector configured to receive the second portion of the drying gas and to determine a real time property of the second portion of the drying gas, and a control unit configured to control a feedback operation of the wafer drying station based on the real time property of the second portion of the drying gas.
    Type: Application
    Filed: March 29, 2021
    Publication date: July 15, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chun HSU, Sheng-Wei Wu, Shu-Yen Wang
  • Patent number: 10962285
    Abstract: A wafer drying method to detect airborne molecular contaminants in a drying gas as a feedback parameter for a single wafer or multi-wafer drying process is provided. For example, the method includes dispensing in a wafer drying station a drying gas over one or more wafers; collecting the drying gas from an exhaust of the wafer drying station; determining the concentration of contaminants in the drying gas; re-dispensing the drying gas over the one or more wafers if the concentration of contaminants is higher than a baseline value; and transferring the one or more wafers out of the wafer drying station if the concentration is equal to or less than the baseline value.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chun Hsu, Sheng-Wei Wu, Shu-Yen Wang
  • Patent number: 10943804
    Abstract: The present disclosure describes a method for controlling a wet processing system includes dispensing one or more chemicals into a processing chamber according to one or more process parameters. The method also includes injecting one or more illumination markers into the processing chamber and obtaining images representing locations of the one or more illumination markers. The method further includes determining a trajectory of an illumination marker of the one or more illumination markers based on the images and determining whether the determined trajectory is outside a predetermined trajectory range. In response to the determined trajectory being outside the predetermined trajectory range, the method further includes adjusting the one or more process parameters.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Chen Chen, Sheng-Wei Wu, Yung-Li Tsai
  • Publication number: 20200135501
    Abstract: The present disclosure is directed to a wafer drying method that detects molecular contaminants in a drying gas as a feedback parameter for a multiple wafer drying process. For example, the method includes dispensing, in a wafer drying module, a drying gas over a batch of wafers. Further, the method includes collecting the drying gas from an exhaust of the wafer drying module and determining the concentration of contaminants in the drying gas. The method also includes re-dispensing the drying gas over the batch of wafers if the concentration of contaminants is greater than a baseline value and transferring the batch of wafers out of the wafer drying module if the concentration is equal to or less than the baseline value.
    Type: Application
    Filed: May 24, 2019
    Publication date: April 30, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chun HSU, Sheng-Wei Wu, Shu-Yen Wang
  • Publication number: 20200055099
    Abstract: The present disclosure relates to an apparatus and a method for wafer cleaning. The apparatus can include a wafer holder configured to hold a wafer; a cleaning nozzle configured to dispense a cleaning fluid onto a first surface (e.g., front surface) of the wafer; and a cleaning brush configured to clean a second surface (e.g., back surface) of the wafer. Using the cleaning fluid, the cleaning brush can clean the second surface of the wafer with a scrubbing motion and ultrasonic vibration.
    Type: Application
    Filed: August 6, 2019
    Publication date: February 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo Chen CHEN, Sheng-Wei WU, Yung-Li TSAI
  • Publication number: 20200018549
    Abstract: The present disclosure is directed to a wafer drying method that detects airborne molecular contaminants in a drying gas as a feedback parameter for a single wafer or multi-wafer drying process. For example, the method includes dispensing in a wafer drying station a drying gas over one or more wafers; collecting the drying gas from an exhaust of the wafer drying station; determining the concentration of contaminants in the drying gas; re-dispensing the drying gas over the one or more wafers if the concentration of contaminants is higher than a baseline value; and transferring the one or more wafers out of the wafer drying station if the concentration is equal to or less than the baseline value.
    Type: Application
    Filed: July 13, 2018
    Publication date: January 16, 2020
    Inventors: Wei-Chun HSU, Sheng-Wei WU, Shu-Yen WANG
  • Publication number: 20200006104
    Abstract: The present disclosure relates to a contamination controlled semiconductor processing system. The contamination controlled semiconductor processing system includes a processing chamber, a contamination detection system, and a contamination removal system. The processing chamber is configured to process a wafer. The contamination detection system is configured to determine whether a contamination level on a surface of the door is greater than a baseline level. The contamination removal system is configured to remove contaminants from the surface of the door in response to the contamination level being greater than the baseline level.
    Type: Application
    Filed: June 10, 2019
    Publication date: January 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo Chen Chen, Sheng-Wei Wu, Yung-Li Tsai
  • Publication number: 20200006101
    Abstract: The present disclosure describes a method for controlling a wet processing system includes dispensing one or more chemicals into a processing chamber according to one or more process parameters. The method also includes injecting one or more illumination markers into the processing chamber and obtaining images representing locations of the one or more illumination markers. The method further includes determining a trajectory of an illumination marker of the one or more illumination markers based on the images and determining whether the determined trajectory is outside a predetermined trajectory range. In response to the determined trajectory being outside the predetermined trajectory range, the method further includes adjusting the one or more process parameters.
    Type: Application
    Filed: June 27, 2019
    Publication date: January 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo Chen CHEN, Sheng-Wei Wu, Yung-Li Tsai
  • Patent number: 9605345
    Abstract: A vertical furnace includes a heat treatment tube, at least one reactive gas inlet, first adiabatic plates and second adiabatic plates. The at least one reactive gas inlet is disposed at or near a bottom end of the heat treatment tube. The first adiabatic plates are stacked in the heat treatment tube, each of the first adiabatic plates having a flow channel structure for allowing a gas to pass through, in which all the corners in the flow channel structure are rounded. The second adiabatic plates are stacked below the first adiabatic plates in the heat treatment tube.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: March 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Eddy Lay, Shih-Min Tseng, Sheng-Wei Wu, Jen-Chung Chen, Shih-Fang Chen
  • Patent number: 9461404
    Abstract: A connector is provided, including a connector body, a fastener and an elastomer. The fastener is pivoted on the connector body with a hook end and a press end positioned on both sides thereof, respectively. The two ends of the elastomer contact the connector body and the press end of the fastener, respectively. The connector of the invention may accomplish plugging and unplugging of an electronic equipment in a single hand press way without bracer arrangement by a configuration of the press end, and may maintain an engagement state between the hook end and the electronic equipment with an arrangement of the elastomer.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: October 4, 2016
    Assignee: FORMERICA OPTOELECTRONICS INC.
    Inventors: Tung-Yi Yu, Sheng-Wei Wu
  • Patent number: 9325417
    Abstract: An optical-electrical converter includes a converter body, two optical-electrical conversion modules and a housing. One end of the converter body is provided with an optical fiber insertion port. The optical-electrical conversion modules are arranged on two sides of the converter body to perform conversion of optical-electrical signal, respectively. The housing is used for covering a portion of the converter body to shield the optical-electrical conversion modules. Because of multiple optical-electrical conversion modules provided by the optical-electrical converter, the arrangement number and volume of the optical-electrical converter in optical fiber network equipment may be reduced significantly to comply with the miniaturization trend of optical fiber network equipment.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: April 26, 2016
    Assignee: FORMERICA OPTOELECTRONICS INC.
    Inventors: Tung-Yi Yu, Sheng-Wei Wu, Chien-Te Cheng