Abstract: A light field display apparatus includes a display element and a switching element. The display element has a plurality of pixels. The switching element is disposed on the display element. The switching element includes a polarizer, a liquid crystal layer, and a metalens array. The metalens array has a plurality of metalens units overlapping the plurality of pixels. The polarizer, the liquid crystal layer, and the metalens array are sequentially disposed on the plurality of pixels of the display element.

Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).

Abstract: A physical vapor deposition (PVD) system is provided. The PVD system includes a PVD chamber defining a PVD volume within which a target material of a target is deposited onto a wafer. The PVD system includes the target in the PVD chamber. The target is configured to overlie the wafer. An edge of the target extends from a first surface of the target to a second surface of the target, opposite the first surface of the target. A first portion of the edge of the target has a first surface roughness. The first portion of the edge of the target extends at most about 6 millimeters from the first surface of the target to a second portion of the edge of the target. The second portion of the edge of the target has a second surface roughness less than the first surface roughness.

Abstract: A semiconductor memory structure includes a ferroelectric layer and a channel layer formed over the ferroelectric layer. The structure also includes a source structure and a drain structure formed over the channel layer. The structure further includes a first isolation structure formed between the source structure and the drain structure. The source structure extends over the cap layer and towards the drain structure.

Abstract: A resistor-transistor-logic circuit with GaN structures, including a 2DEG resistor having a drain connected with an operating voltage, and a logic FET having a gate connected to an input voltage, a source grounded and a drain connected with a source of the 2DEG resistor and connected collectively to an output voltage.

Abstract: A resistor with GaN structures, including a GaN layer with a 2DEG resistor region and an undoped polysilicon resistor region, an AlGaN barrier layer on the GaN layer in the 2DEG resistor region, multiple p-type doped GaN capping layers arranged on the AlGaN barrier layer so that the GaN layer not covered by the p-type doped GaN capping layers in the 2DEG resistor region is converted into a 2DEG resistor, a passivation layer on the GaN layer, and an undoped polysilicon layer on the passivation layer in the undoped polysilicon resistor region and functions as an undoped polysilicon resistor.

Abstract: Some implementations described herein provide techniques and apparatuses for forming a stacked die product including two or more integrated circuit dies. A bond interface between two integrated circuit dies that are included in the stacked die product includes a layered structure. As part of the layered structure, respective layers of a sealant material are directly on co-facing surfaces of the two integrated circuit dies. The layered structure further includes one or more bonding layers between the respective layers of the sealant material that are directly on the co-facing surfaces of the two integrated circuit dies. The layered structure may reduce lateral stresses throughout the bond interface to reduce a likelihood of warpage of the two integrated circuit dies.

Abstract: An anti-scattering and anti-interference coating pattern structure of an optical film, wherein an optical film is formed on a substrate, the characterize is: the periphery of the optical film is a non-straight zigzag lines or multi-curved inner edge lines, such that can be used to reduce stray light affecting the sensing area when it is used in light-sensing components.

Abstract: The present disclosure relates to an integrated chip including a three-dimensional memory array. The three-dimensional memory array includes a first local line and a second local line that are elongated vertically, a first memory cell extending between the first local line and the second local line, and a second memory cell directly under the first memory cell, extending between the first local line and the second local line, and coupled in parallel with the first memory cell. The first memory cell is coupled to a first word line and the second memory cell is coupled to a second word line. The first word line and the second word line are elongated horizontally. A first global line is disposed at a first height and is elongated horizontally. A first selector extends vertically from the first local line to the first global line.

Abstract: An alarm system an alarm method for a medical emergency are provided. The alarm method includes: obtaining a physiological signal of a user by a sensor of a portable electronic device; receiving the physiological signal from the portable electronic device, determining whether an abnormal event has occurred according to the physiological signal, and transmitting first feedback information corresponding to the physiological signal to a server in response to the abnormal event by the terminal device; and outputting an alarm message according to the first feedback information by the server.

Abstract: The present disclosure relates to a contamination controlled semiconductor processing system. The contamination controlled semiconductor processing system includes a processing chamber, a contamination detection system, and a contamination removal system. The processing chamber is configured to process a wafer. The contamination detection system is configured to determine whether a contamination level on a surface of the door is greater than a baseline level. The contamination removal system is configured to remove contaminants from the surface of the door in response to the contamination level being greater than the baseline level.

Abstract: An image sensor includes a first unit. The first unit includes a first photodiode having a first dimension, a second photodiode disposed adjacent the first photodiode and having a second dimension that is greater than the first dimension, a first color filter overlapping the first photodiode and the second photodiode, and a first internal reflector disposed in the first color filter and overlapping the first photodiode. The first internal reflector has an inclined light receiving surface inclined from a top surface of the first color filter toward the second photodiode, and a refraction index of the first internal reflector is smaller than a refraction index of the first color filter.

Abstract: A probe card includes a structure stiffener unit including a base with a lower surface where central and peripheral supporting elements protrude out and a main circuit board is fixed, a space transformer and a probe head disposed thereunder, which are disposed to the supporting elements by bolts and defined with central and peripheral regions located correspondingly to the central and peripheral supporting elements respectively, and a metal supporting member fixed on the space transformer in a direct contact manner and located correspondingly to the central region. The supporting member has a lower surface coplanar with the lower end surface of the peripheral supporting element, which is abutted on the space transformer, and an upper surface against which the central supporting element is abutted. The space transformer has great structural strength, flatness and heat dissipation effect for satisfying the large-area requirement and great electrical property testing stability.

Abstract: The present disclosure relates to a contamination controlled semiconductor processing system. The contamination controlled semiconductor processing system includes a processing chamber, a contamination detection system, and a contamination removal system. The processing chamber is configured to process a wafer. The contamination detection system is configured to determine whether a contamination level on a surface of the door is greater than a baseline level. The contamination removal system is configured to remove contaminants from the surface of the door in response to the contamination level being greater than the baseline level.

Abstract: The present disclosure relates to an apparatus and a method for wafer cleaning. The apparatus can include a wafer holder configured to hold a wafer; a cleaning nozzle configured to dispense a cleaning fluid onto a first surface (e.g., front surface) of the wafer; and a cleaning brush configured to clean a second surface (e.g., back surface) of the wafer. Using the cleaning fluid, the cleaning brush can clean the second surface of the wafer with a scrubbing motion and ultrasonic vibration.

Abstract: The present disclosure relates to an apparatus and a method for wafer cleaning. The apparatus can include a wafer holder configured to hold a wafer; a cleaning nozzle configured to dispense a cleaning fluid onto a first surface (e.g., front surface) of the wafer; and a cleaning brush configured to clean a second surface (e.g., back surface) of the wafer. Using the cleaning fluid, the cleaning brush can clean the second surface of the wafer with a scrubbing motion and ultrasonic vibration.

Abstract: The present disclosure is directed to a wafer drying system and method that detects airborne molecular contaminants in a drying gas as a feedback parameter for a single wafer or multi-wafer drying process. For example, the system comprises a wafer drying station configured to dispense a drying gas over one or more wafers to dry the one or more wafers, a valve configured to divert the drying gas to a first portion and a second portion, and an exhaust line configured to exhaust the first portion of the drying gas. The system further comprises a detector configured to receive the second portion of the drying gas and to determine a real time property of the second portion of the drying gas, and a control unit configured to control a feedback operation of the wafer drying station based on the real time property of the second portion of the drying gas.

Abstract: The present disclosure is directed to a wafer drying system and method that detects airborne molecular contaminants in a drying gas as a feedback parameter for a single wafer or multi-wafer drying process. For example, the system comprises a wafer drying station configured to dispense a drying gas over one or more wafers to dry the one or more wafers, a valve configured to divert the drying gas to a first portion and a second portion, and an exhaust line configured to exhaust the first portion of the drying gas. The system further comprises a detector configured to receive the second portion of the drying gas and to determine a real time property of the second portion of the drying gas, and a control unit configured to control a feedback operation of the wafer drying station based on the real time property of the second portion of the drying gas.

Abstract: The present disclosure relates to an apparatus and a method for wafer cleaning. The apparatus can include a wafer holder configured to hold a wafer; a cleaning nozzle configured to dispense a cleaning fluid onto a first surface (e.g., front surface) of the wafer; and a cleaning brush configured to clean a second surface (e.g., back surface) of the wafer. Using the cleaning fluid, the cleaning brush can clean the second surface of the wafer with a scrubbing motion and ultrasonic vibration.

Abstract: A semiconductor device manufacturing system and a method for manufacturing semiconductor device are provided. The semiconductor device manufacturing system includes a substrate processing device and a processor. The substrate processing device includes a processing chamber, a gas supply module and a gas source. The processor is configured to monitor and control the gas supplied into the substrate processing device.