Patents by Inventor Sheng Wei

Sheng Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SOLUBLE CD33 FOR TREATING MYELODYSPLASTIC SYNDROMES (MDS)
    Publication number: 20200055916
    Abstract: Disclosed are compositions and methods for treating disease or condition caused or exacerbated by S100A9 activity, such as myelodysplastic syndromes (MDS) using a composition comprising an effective amount of a CD33/S100A9 inhibitor.
    Type: Application
    Filed: June 25, 2019
    Publication date: February 20, 2020
    Inventors: Alan F. List, Sheng Wei
  • MESH RENDERING SYSTEM, MESH RENDERING METHOD AND NON-TRANSITORY COMPUTER READABLE MEDIUM
    Publication number: 20200051308
    Abstract: A mesh rendering system, a mesh rendering method and a non-transitory computer readable medium are provided. The mesh rendering system includes a database, a user device and a server. The server obtains preprocessing data of a cloth and a rigidbody according to initial mesh state of the cloth, initial mesh state of the rigidbody and motion of the rigidbody, wherein the cloth and the rigidbody are deformable and motion of the cloth corresponding to the motion of the rigidbody is a small deformation. The server stores the preprocessing data in the database. A finite state machine of the server receives a real-time input data from the user device through a web service and the preprocessing data, and the finite state machine outputs a deformation result of the cloth and the rigidbody to the user device through a handshake mechanism.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 13, 2020
    Inventors: Sheng-Yen Lin, Sheng-Wei Lin, Ching-Tung Lin, Jui-Fen Ho
  • Threshold Voltage Adjustment for a Gate-All-Around Semiconductor Structure
    Publication number: 20200035562
    Abstract: A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.
    Type: Application
    Filed: October 7, 2019
    Publication date: January 30, 2020
    Inventors: Hung-Li Chiang, Szu-Wei Huang, Huan-Sheng Wei, Jon-Hsu Ho, Chih Chieh Yeh, Wen-Hsing Hsieh, Chung-Cheng Wu, Yee-Chia Yeo
  • Redistribution layer structure and fabrication method therefor
    Patent number: 10541218
    Abstract: A method of manufacturing a semiconductor device includes depositing a first passivation layer over a substrate, depositing a conductive material over the first passivation layer, patterning the conductive material to form a redistribution layer (RDL) structure, and depositing a second passivation layer configured to change a shape of a top portion of the RDL structure.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: January 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Anhao Cheng, Chun-Chang Liu, Sheng-Wei Yeh
  • WAFER DRYING SYSTEM
    Publication number: 20200018549
    Abstract: The present disclosure is directed to a wafer drying method that detects airborne molecular contaminants in a drying gas as a feedback parameter for a single wafer or multi-wafer drying process. For example, the method includes dispensing in a wafer drying station a drying gas over one or more wafers; collecting the drying gas from an exhaust of the wafer drying station; determining the concentration of contaminants in the drying gas; re-dispensing the drying gas over the one or more wafers if the concentration of contaminants is higher than a baseline value; and transferring the one or more wafers out of the wafer drying station if the concentration is equal to or less than the baseline value.
    Type: Application
    Filed: July 13, 2018
    Publication date: January 16, 2020
    Inventors: Wei-Chun HSU, Sheng-Wei WU, Shu-Yen WANG
  • CONTAMINATION CONTROL IN SEMICONDUCTOR MANUFACTURING SYSTEMS
    Publication number: 20200006104
    Abstract: The present disclosure relates to a contamination controlled semiconductor processing system. The contamination controlled semiconductor processing system includes a processing chamber, a contamination detection system, and a contamination removal system. The processing chamber is configured to process a wafer. The contamination detection system is configured to determine whether a contamination level on a surface of the door is greater than a baseline level. The contamination removal system is configured to remove contaminants from the surface of the door in response to the contamination level being greater than the baseline level.
    Type: Application
    Filed: June 10, 2019
    Publication date: January 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo Chen Chen, Sheng-Wei Wu, Yung-Li Tsai
  • MONITORING OF PROCESS CHAMBER
    Publication number: 20200006101
    Abstract: The present disclosure describes a method for controlling a wet processing system includes dispensing one or more chemicals into a processing chamber according to one or more process parameters. The method also includes injecting one or more illumination markers into the processing chamber and obtaining images representing locations of the one or more illumination markers. The method further includes determining a trajectory of an illumination marker of the one or more illumination markers based on the images and determining whether the determined trajectory is outside a predetermined trajectory range. In response to the determined trajectory being outside the predetermined trajectory range, the method further includes adjusting the one or more process parameters.
    Type: Application
    Filed: June 27, 2019
    Publication date: January 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo Chen CHEN, Sheng-Wei Wu, Yung-Li Tsai
  • SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME
    Publication number: 20190386132
    Abstract: A method for forming a semiconductor device is provided. A plurality of trenches are formed in the substrate. An isolation oxide layer is formed in the trenches and on the substrate. A shield polysilicon is deposited in the trenches and on the isolation oxide layer on the substrate. A first etching process is performed to remove a first portion of the shield polysilicon. A first removal process is performed to remove a first portion of the isolation oxide layer. A second etching process is performed to remove a second portion of the shield polysilicon. A second removal process is performed to remove a second portion of the isolation oxide layer. An inter-poly oxide layer is formed on the remaining shield polysilicon and the remaining isolation oxide layer, wherein the inter-poly oxide layer has a concave top surface.
    Type: Application
    Filed: June 13, 2018
    Publication date: December 19, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chung-Yen CHIEN, Sheng-Wei FU, Chung-Yeh Lee
  • Semiconductor devices and methods for forming the same
    Patent number: 10510878
    Abstract: A method for forming a semiconductor device is provided. A plurality of trenches are formed in the substrate. An isolation oxide layer is formed in the trenches and on the substrate. A shield polysilicon is deposited in the trenches and on the isolation oxide layer on the substrate. A first etching process is performed to remove a first portion of the shield polysilicon. A first removal process is performed to remove a first portion of the isolation oxide layer. A second etching process is performed to remove a second portion of the shield polysilicon. A second removal process is performed to remove a second portion of the isolation oxide layer. An inter-poly oxide layer is formed on the remaining shield polysilicon and the remaining isolation oxide layer, wherein the inter-poly oxide layer has a concave top surface.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: December 17, 2019
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chung-Yen Chien, Sheng-Wei Fu, Chung-Yeh Lee
  • SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME
    Publication number: 20190378902
    Abstract: A semiconductor device and methods for forming the same are provided. The method includes providing a substrate having a first conductive type, forming an epitaxial layer having the first conductive type on the substrate, forming a trench in the epitaxial layer, forming a first insulating layer in the trench and on the top surface of the epitaxial layer, forming a shield electrode and a mask layer on the first insulating layer in order, using the mask layer to remove a portion of the first insulating layer, wherein the top surface of the first insulating layer is higher than the top surface of the shield electrode after removing the portion of the first insulating layer, removing the mask layer, forming a second insulating layer on the first insulating layer and the shield electrode, and forming a gate electrode on the second insulating layer.
    Type: Application
    Filed: June 11, 2018
    Publication date: December 12, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Tsung-Yeh CHEN, Sheng-Wei FU, Chung-Yeh LEE
  • REFERENCE VOLTAGE GENERATOR WITH ADAPTIVE VOLTAGE AND POWER CIRCUIT
    Publication number: 20190379286
    Abstract: There is provided a reference voltage generator for providing an adaptive voltage. The reference voltage generator includes a steady current source and a PMOS transistor and an NMOS transistor cascaded to each other. A reference voltage provided by the reference voltage generator is determined by gate-source voltages of the PMOS transistor and the NMOS transistor. As said gate-source voltages vary with the temperature and manufacturing process, the reference voltage forms a self-adaptive voltage.
    Type: Application
    Filed: August 21, 2019
    Publication date: December 12, 2019
    Inventor: LIEN-SHENG WEI
  • Method, processing circuit, and wireless communication device capable of tuning current provided for DCO to lower current level as far as possible
    Patent number: 10491226
    Abstract: A method for tuning a current source of a digitally controlled oscillator having an LC tank having a tunable capacitor bank includes: determining a specific threshold according to a resolution of a bit number of the tunable capacitor bank; configuring a current flowing through the current source at a first current level; tuning the current flowing through the current source from the first current level to a lower current level; comparing a variation of a digital value of the tunable capacitor bank with the specific threshold, the digital value corresponding to the lower current level; and determining that a current level required by the digitally controlled oscillator is decreased down to the lower current level and then configuring the current flowing through the current source at the lower current level if the variation of the digital value is smaller than the specific threshold.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: November 26, 2019
    Assignee: Audiowise Technology Inc.
    Inventor: Lien-Sheng Wei
  • METHOD FOR FABRICATING MEMS DEVICE INTEGRATED WITH A SEMICONDUCTOR INTEGRATED CIRCUIT
    Publication number: 20190345029
    Abstract: A method for fabricating a semiconductor device is disclosed. A semiconductor substrate comprising a MOS transistor is provided. A MEMS device is formed over the MOS transistor. The MEMS device includes a bottom electrode in a second topmost metal layer, a diaphragm in a pad metal layer, and a cavity between the bottom electrode and the diaphragm.
    Type: Application
    Filed: July 25, 2019
    Publication date: November 14, 2019
    Inventors: Tsong-Lin Shen, Chien-Chung Su, Chih-Cheng Wang, Yu-Chih Chuang, Sheng-Wei Hung, Min-Hung Wang, Chin-Tsai Chang
  • MEMS device integrated with a semiconductor integrated circuit and manufacturing method thereof
    Patent number: 10472232
    Abstract: A semiconductor device includes a semiconductor substrate comprising a MOS transistor. A MEMS device is integrally constructed above the MOS transistor. The MEMS device includes a bottom electrode in a second topmost metal layer, a diaphragm in a pad metal layer, and a cavity between the bottom electrode and the diaphragm.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: November 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsong-Lin Shen, Chien-Chung Su, Chih-Cheng Wang, Yu-Chih Chuang, Sheng-Wei Hung, Min-Hung Wang, Chin-Tsai Chang
  • Automatic camera configuration using a fiducial marker
    Patent number: 10453216
    Abstract: Systems and associated methods are disclosed for automatically configuring cameras to be associated with a known physical location in response to exposing the camera to a fiducial marker. In certain embodiments, boundaries for a zone of interest within images from the camera can be defined using the fiducial markers physically placed within the physical space.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: October 22, 2019
    Assignee: Amazon Technologies
    Inventors: Lev Zelenskiy, Jon Robert Ducrou, Alexander Edwards, Tony Li, Sheng-Wei Lin, Stephen Waits
  • Optical imaging lens
    Patent number: 10451855
    Abstract: The present disclosure provides for various embodiments of optical imaging lenses. An optical imaging lens may comprise six lens elements positioned in an order from an object side to an image side. By controlling the convex or concave shape of the surfaces of the lens elements, the optical imaging lens may provide great view angle and proper length of the optical imaging lens and improve the imaging quality.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: October 22, 2019
    Assignee: Genius Electronic Optical Co., LTD.
    Inventors: Yu-Ming Chen, Sheng-Wei Hsu, Pei-Chi Wang
  • TLR9-BINDING CHIMERIC ANTIGEN RECEPTORS
    Publication number: 20190309086
    Abstract: Disclosed herein are chimeric antigen receptor (CAR) polypeptides that can be used with adoptive cell transfer to target and kill cancer cells that express TLR9 on their surface. Also disclosed are immune effector cells, such as T cells or Natural Killer (NK) cells that are engineered to express these CARs. Therefore, also disclosed are methods of providing an anti-tumor immunity in a subject with a TLR9-expressing cancer that involves adoptive transfer of the disclosed immune effector cells engineered to express the disclosed CARs.
    Type: Application
    Filed: December 8, 2017
    Publication date: October 10, 2019
    Inventors: Daniel Abate-Daga, Alan F. List, Sheng Wei
  • Threshold voltage adjustment for a gate-all-around semiconductor structure
    Patent number: 10438851
    Abstract: A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: October 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Li Chiang, Szu-Wei Huang, Huan-Sheng Wei, Jon-Hsu Ho, Chih Chieh Yeh, Wen-Hsing Hsieh, Chung-Cheng Wu, Yee-Chia Yeo
  • SELF-ADAPTIVE WEB CRAWLING AND TEXT EXTRACTION
    Publication number: 20190303501
    Abstract: A method, computer system, and a computer program product for crawling and extracting main content from a web page is provided. The present invention may include retrieving a HTML document associated with a web page. The present invention may then include identifying at least one entry point located in the retrieved HTML document by utilizing a self-adaptive entry point locator. The present invention may also include extracting a main content article associated with the retrieved HTML document based on the identified at least one entry point. The present invention may further include presenting the extracted main content associated with the retrieved HTML document to the user.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 3, 2019
    Inventors: Chen-Yu Huang, Sheng-Wei Lee, June-Ray Lin, Ci-Hao Wu, Hsieh-Lung Yang, Ying-Chen Yu
  • Redistribution Layer Metallic Structure and Method
    Publication number: 20190304939
    Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 3, 2019
    Inventors: Shih Wei Bih, Sheng-Wei Yeh, Yen-Yu Chen, Wen-Hao Cheng, Chih-Wei Lin, Chun-Chih Lin