Abstract: Methods and systems for multi-path video and network channels may comprise a communication device comprising a wideband tuner (WB) and a narrowband tuner (NB). A video channel and a network channel may be received in the WB when the device is operating in a first stage. A video channel and a network channel may be received in the WB and the network channel may also be received in the NB when the device is operating in a second stage. The network channel may be received in the NB when the device is operating in a third stage. The reception of the network channel from both the WB and NB may enable a continuous reception of the network channel in a transition between the first and third stages. The WB may be operable to receive a plurality of channels and the NB may be operable to receive a single channel.

Abstract: A curable composition having a polythiol; at least one unsaturated compound comprising more than one carbon-carbon double bond, carbon-carbon triple bond, or a combination thereof; and a dye compound represented by formula (I). A crosslinked composition prepared from the curable composition, a method of making an at least partially crosslinked network, a method for indicating curing in a curable composition, and a method of stabilizing a curable composition comprising a polythiol and at least one unsaturated compound comprising more than one carbon-carbon double bond, carbon-carbon triple bond, or a combination thereof are also disclosed. Z is not reactive with the polythiol or unsaturated compound.

Abstract: Methods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch.

Abstract: Systems and methods are provided for jitter improvement in serializer-deserializer (SerDes) transmitters. One or more adjustments may be applied in SerDes transmitter circuitry to reduce jitter in a serial output of the SerDes transmitter circuitry, which may occur as a result of processing of input data. Applying the one or more adjustments may comprise use of dummy data. The dummy data may be configured to generate corresponding dummy current pulses which may in turn be used in controlling supply variations occurring during processing of the input data and/or generation of the serial output. The dummy data may be configured to generate the dummy current pulses such that they are applied along with current pulses corresponding to the input data. The dummy data may be adaptively set or adjusted based on the input data. The use of the dummy data may be selectively turned on or off.

Abstract: The present invention discloses an electrolytic water urinal. The electrolytic water urinal includes an electrolysis module and a urinal body. The electrolysis module produces the acidic electrolytic water and the alkaline electrolytic water. The electrolysis module includes a first water outlet and a second water outlet. The urinal body includes a bowl water inlet which is provided on an upper portion of the urinal body. The first water outlet and the second water outlet of the electrolysis module are connected to the bowl water inlet of the urinal body. The acidic electrolytic water and the alkaline electrolytic water produced by the electrolysis module are sprayed on an inner wall of the urinal body alternately or simultaneously through the bowl water inlet so as to perform washing from top to bottom.

Abstract: Provided are devices for applying actinic radiation to a curable resin. The devices include a housing having a front face, an actinic radiation source arranged within the housing such that actinic radiation emerges from the housing through the front face, and a proximity detector. The proximity detector is functionally connected to the actinic radiation source such that the actinic radiation source is shut off unless the proximity detector detects the presence of a surface within a safe distance from the front face. Optionally, the device includes a surface temperature sensor functionally connected to the actinic radiation source such that the actinic radiation source is shut off if the surface temperature sensor senses a surface temperature exceeding a maximum safe surface temperature.

Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

Abstract: Methods of bonding hardware to glass and other substrates are provided that do not require use of primers, mixing, fixturing, or autoclaving. These methods include the steps of disposing an adhesive layer on a bonding surface of either the hardware or the vehicular glass, the adhesive layer comprising a curable composition that is dimensionally stable at ambient conditions; either before or after disposing the adhesive layer on the bonding surface, irradiating the adhesive layer with ultraviolet radiation to initiate curing of the curable composition; placing the hardware so as to be bonded to the vehicular glass by the adhesive layer; and allowing the adhesive layer to cure.

Abstract: A communication receiver which applies signal processing for quantitatively estimating receive signal factors such as communication channel quality, signal characteristics, and overall system received bit error rate (BER) or packet error rate (PER) and which applies a general algorithm for mapping these estimated factors to control receiver performance and minimize power consumption.

Abstract: A composition including a polythiol having more than one thiol groups, a polyepoxide having more than one epoxide group, a catalytic amount of a second amine, and a photolatent base catalyst. The photolatent base catalyst can photochemically generate a first amine, which may be the same as or different from the second amine. A polymer network preparable from the composition, and a method for making the polymer network are also disclosed.

Abstract: A phase locked loop may be operable to generate, utilizing a frequency multiplier, a reference clock signal whose frequency is an integer M times a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. The phase locked loop may enable usage of both rising and falling edges of the crystal clock signal, based on the reference clock signal. The phase locked loop may perform an operation of the phase locked loop based on the enabling. The phase locked loop may perform a phase comparison function, based on both rising and falling edges of the crystal clock signal. By utilizing a sampled loop filter in the phase locked loop, the phase locked loop may eliminate, at an output of a charge pump in the phase locked loop, disturbance which is associated with duty cycle errors of the crystal clock signal.

Abstract: A method of making a polymer network. The method includes providing a composition including a polythiol having more than one thiol group and a polyepoxide having more than one epoxide group, applying a solution including a photolatent base catalyst to a surface of the composition, and subsequently exposing the composition to light. Upon exposure to light, the photolatent base catalyst photochemically generates a first amine and at least partially cures at least the surface of the composition to form the polymer network.

Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals.

Abstract: Methods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch.

Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

Abstract: Compositions that are curable to polythioether polymers are provided, comprising: a) a dithiol monomer; b) a diene monomer; c) a radical cleaved photoinitiator; d) a peroxide; and e) an amine; where the peroxide and amine together are a peroxide-amine redox initiator. In some embodiments, the amine is a tertiary amine. In some embodiments, the amine is selected from the group consisting of dihydroxyethyl-p-toluidine, N,N-diisopropylethylamine, and N, N, N?, N?, N?-pentamethyl-diethylenetriamine. In some embodiments, the peroxide is selected from the group consisting of di-tert-butyl peroxide, methyl ethyl ketone peroxide, and benzoyl peroxide. In some embodiments, the composition may additionally comprise a polythiol monomer having three or more thiol groups.

Abstract: A phase locked loop may be operable to generate, utilizing a frequency doubler, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. A sampled loop filter (SLPF) in the phase locked loop may capture charge from a charge pump (CHP) in the phase locked loop and the charge is captured at a frequency corresponding to the frequency of the reference clock signal. Opening a switch of the SLPF may hold the captured charge during a phase comparison and closing the switch may release the captured charge. The switch is controlled utilizing a control signal. By utilizing the SLPF in the phase locked loop, the phase locked loop may eliminate, at an output of the CHP, disturbance which is associated with duty cycle errors of the crystal clock signal.

Abstract: A system for processing signals may be configured to detect occurrence of particular errors, comprising meta-stability events, during digital conversion to analog signals, and to handle any detected meta-stability event, such as by adjusting at least a portion of a corresponding digital output based on detection of the meta-stability event. The adjusting of the digital output may comprise setting at least the portion of the digital output, such as to one of a plurality of predefined digital values or patterns. The system may comprise a code generator for generating and/or outputting the predefined digital values or patterns. The system may comprise a selector for adaptively selecting, for portions of the digital output, between output of normal processing path and between predefined values or patterns.

Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals.

Abstract: Each of a plurality of modules comprises a respective one of a plurality of antenna elements, and each of a subset of the plurality of modules comprising a respective one of a plurality of transceivers, wherein the plurality of modules are interconnected via one or more communication links. The circuitry may be operable to receive a calibration signal via the plurality of antenna elements, determine, for each one of the antenna elements, a time and/or phase of arrival of the calibration signal, calculate, based on the time and/or phase of arrival of the calibration signal at each of the plurality of antenna elements, electrical distances between the plurality of antenna elements on the one or more communication links, and calculate beamforming coefficients for use with the plurality of antenna elements based on the electrical distances.