Patents by Inventor Sheng Yi
Sheng Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12276103Abstract: A stirrup module includes a bottom rib and a first erect bar, a second erect bar, a third erect bar and a fourth erect bar that are arranged in parallel to each other. The third erect bar is located between the first erect bar and the second erect bar. The fourth erect bar is located between the third erect bar portion and the second erect bar portion. A first gap is between the first erect bar and the third erect bar, and a second gap is between the second erect bar and the fourth erect bar. The bottom rib connects the bottom ends of the first erect bar, the second erect bar, the third erect bar and the fourth erect bar, and the first gap and the second gap are each formed with an opening at the end opposite to the bottom rib.Type: GrantFiled: October 6, 2022Date of Patent: April 15, 2025Assignee: CHIEN KUO CONSTRUCTION CO., LTD.Inventors: Chang-Shiou Wu, Sheng-Yi Yen, Chia-Hsuan Huang
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Patent number: 12221786Abstract: A stirrup module includes an outer stirrup set, an upper-opening stirrup set having an upper opening and provided in an opening of the outer stirrup of the outer stirrup set, and a lower-opening stirrup set having a lower opening and provided in the opening of the outer stirrup of the outer stirrup set. Wherein the upper opening and the opening of the outer stirrup are oriented in the same direction, the lower opening and the upper opening are in opposite directions to each other. Wherein the upper-opening stirrup set has a first bottom of stirrup opposite to the upper opening, and the first bottom of stirrup corresponds to the position of the lower opening; the lower-opening stirrup set has a second bottom rib opposite to the lower opening, and the second bottom rib corresponds to the position of the upper opening.Type: GrantFiled: October 12, 2022Date of Patent: February 11, 2025Assignee: CHIEN KUO CONSTRUCTION CO., LTD.Inventors: Chang-Shiou Wu, Sheng-Yi Yen, Chia-Hsuan Huang
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Patent number: 12198054Abstract: The performance of a neural network (NN) and/or deep neural network (DNN) can limited by the number of operations being performed as well as management of data among the various memory components of the NN/DNN. A sparsity-inducing regularization optimization process is performed on a machine learning model to generate a compressed machine learning model. A machine learning model is trained using a first set of training data. A sparsity-inducing regularization optimization process is executed on the machine learning model. Based on the sparsity-inducing regularization optimization process, a compressed machine learning model is received. The compressed machine learning model is executed to generate one or more outputs.Type: GrantFiled: August 30, 2023Date of Patent: January 14, 2025Assignee: Microsoft Technology Licensing, LLCInventors: Tianyi Chen, Sheng Yi, Yixin Shi, Xiao Tu
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Publication number: 20240419748Abstract: Systems and methods are provided for implementing adaptable embedded search engine functionality. In an aspect, a shared SERP system receives a user search query from a first search utility among a plurality of search utilities, which is associated with corresponding apps that are different from each other. A router of the shared SERP system provides the user search query and location information to a first query builder among one or more query builders of the shared SERP system. The first query builder constructs a query request corresponding to the user search query, based on the provided user search query and location information. A first query executor among one or more query executors of the shared SERP system executes the query request to produce search results. A component renderer of the shared SERP system renders one or more UX components within the first SERP, based on the search results.Type: ApplicationFiled: June 16, 2023Publication date: December 19, 2024Applicant: Microsoft Technology Licensing, LLCInventors: Alicia Oliva COLL, Jose Miguel RIVERA DAVALOS, Qiwen GUO, Raghu R. NADIMINTI, Andreas Allern BROSE, Bjørnstein LILLEBY, Steffen Viken VALVÅG, Gordon Bradford JENSEN, Luke ROBERTS, Soujanya SRIVALLI, Jon MELING, Sheng Yi CHOU, Tracey SAUR, Tudor POPA, Mikael SVENSON, Ajla BADZA
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Publication number: 20240378915Abstract: A computer system is provided that includes one or more processors configured to receive user input for inked content to a digital canvas, and process the inked content to determine one or more writing regions. Each writing region includes recognized text and one or more document layout features associated with that writing region. The one or more processors are further configured to tokenize a target writing region of the one or more writing regions into a sequence of tokens, process the sequence of tokens of the target writing region using a task extraction subsystem that operates on tokens representing both the recognized text and the one or more document layout features of the target writing region, segment the target writing region into one or more sentence segments, and classify each of the one or more sentence segments as a task sentence or a non-task sentence.Type: ApplicationFiled: July 25, 2024Publication date: November 14, 2024Applicant: Microsoft Technology Licensing, LLCInventors: Jenna HONG, Apurva Sandeep GANDHI, Gilbert ANTONIUS, Tra My NGUYEN, Ryan SERRAO, Biyi FANG, Sheng YI
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Publication number: 20240376003Abstract: An aggregate (12, 16) is disclosed as including a core (12a) made at least partly of biochar (10, 14, 26, 28), and a shell (12b) encapsulating the core, the shell being made of ordinary portland cement (OPC) and ground granulated blast-furnace slag (GGBS). Structural concrete (30) including such an aggregate is also disclosed.Type: ApplicationFiled: May 8, 2024Publication date: November 14, 2024Inventors: Shuai Zou, Chung Kong Chau, Sheng Yi Lin, Lai Ming Leung, Man Lung Sham
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Patent number: 12093111Abstract: An electronic device and a performance optimization method thereof are provided. The electronic device includes a battery module, a processor, and a controller. The battery module is configured to supply power to the electronic device. The processor has a power limit. The controller is configured to monitor a charging and discharging current of the battery module. In a power connection mode, the controller analyzes a status of the battery module and adjusts the power limit of the processor according to the charging and discharging current.Type: GrantFiled: October 14, 2022Date of Patent: September 17, 2024Assignee: ASUSTeK COMPUTER INC.Inventors: Po-Han Cheng, Chin-Chang Chang, Po-Hsin Chang, Shih-Hao Chen, Kai-Peng Chung, Ci-Syuan Wu, Chun Tsao, Teng-Chih Wang, Sheng-Yi Chen, Guan-Heng Lai
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Patent number: 12087070Abstract: A computer system is provided that includes one or more processors configured to receive user input for inked content to a digital canvas, and process the inked content to determine one or more writing regions. Each writing region includes recognized text and one or more document layout features associated with that writing region. The one or more processors are further configured to tokenize a target writing region of the one or more writing regions into a sequence of tokens, process the sequence of tokens of the target writing region using a task extraction subsystem that operates on tokens representing both the recognized text and the one or more document layout features of the target writing region, segment the target writing region into one or more sentence segments, and classify each of the one or more sentence segments as a task sentence or a non-task sentence.Type: GrantFiled: November 12, 2021Date of Patent: September 10, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Jenna Hong, Apurva Sandeep Gandhi, Gilbert Antonius, Tra My Nguyen, Ryan Serrao, Biyi Fang, Sheng Yi
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Publication number: 20240265833Abstract: An electronic shelf label positioning method and system. The method includes: receiving a binding relationship between a shelf ID and a guide rail ID, and a binding relationship between the guide rail ID and wireless label IDs; receiving the wireless label ID read by the electronic shelf label; determining the guide rail ID of the guide rail where the electronic shelf label is located based on the wireless label ID and the binding relationship between the guide rail ID and the wireless label ID; determining the shelf ID of the commodity shelf where the electronic shelf label is located based on the determined guide rail ID and the binding relationship between the shelf ID and the guide rail ID; and determining a position of the electronic shelf label based on the determined guide rail ID, the determined shelf ID and the wireless label ID.Type: ApplicationFiled: March 13, 2024Publication date: August 8, 2024Inventors: Shiguo HOU, Jianguo ZHAO, Min LIANG, Le ZHUO, Sheng YI, Yang ZHAO, Yanwei WANG, Linjiang WANG
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Patent number: 12006600Abstract: A yarn made from a mixture of a grain and a first polymer by spinning is provides. The yarn includes a plurality of fibers. Each fiber has a surface layer and a core layer surrounded by the surface layer. The surface layer is made from the grain and the first polymer. The core layer is made from the first polymer. The grain includes a nano-powder mixture and a second polymer. A weight percentage of the nano-powder mixture in the grain is from 60% to 70%. The nano-powder mixture includes silicon dioxide, magnesium oxide and aluminum oxide. A weight ratio of silicon dioxide to magnesium oxide in the nano-powder mixture is from 2:1 to 1:2. A weight ratio of silicon dioxide to aluminum oxide in the nano-powder mixture is from 2:1 to 1:2.Type: GrantFiled: November 18, 2021Date of Patent: June 11, 2024Assignee: STAR LACE CO., LTD.Inventor: Sheng-Yi Lin
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Patent number: 12009505Abstract: Provided is a composite layer of graphene sheets and anode particles being dispersed in a conducting polymer network for a lithium battery anode (negative electrode), the layer comprising a mixture of a conducting polymer network, multiple graphene sheets, and multiple particles of an anode active material, wherein the anode particles have a diameter or thickness from 0.5 nm to 20 ?m and occupy from 30% to 98% by weight, the graphene sheets occupy from 0.01% to 25% by weight, and the conducting polymer network occupies from 1% to 30% by weight based on the total mixture weight and wherein the graphene sheets and the conducting polymer network together form dual conducting pathways for both electrons and lithium ions.Type: GrantFiled: May 12, 2020Date of Patent: June 11, 2024Assignee: Honeycomb Battery CompanyInventors: Sheng-Yi Lu, Aruna Zhamu, Bor Z. Jang
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Patent number: 11984580Abstract: Provided is an anode particulate for a lithium battery, the particulate comprising a polymer foam material having pores and a single or a plurality of primary particles of an anode active material embedded in or in contact with said polymer foam material, wherein said primary particles of anode active material have a total solid volume Va, and said pores have a total pore volume Vp, and the volume ratio Vp/Va is from 0.1/1.0 to 10/1.Type: GrantFiled: May 6, 2019Date of Patent: May 14, 2024Assignee: Honeycomb Battery CompanyInventors: Yi-jun Lin, Yen-Po Lin, Sheng-Yi Lu, Bor Z. Jang
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Patent number: 11961423Abstract: An electronic shelf label positioning system, an electronic shelf label and a guide rail. The electronic shelf label positioning system includes the electronic shelf label, the guide rail, a PDA and a background server. The electronic shelf label includes a main control SoC, a card reader IC, a screen and a power supply device. The main control SoC is configured to control the screen display and to communicate with an AP. The power supply device is configured to supply power to the electronic shelf label. The guide rail includes a guide rail identification area and a label area. The label area is installed with a plurality of wireless labels each having a unique non-repeated ID number. The guide rail identification area is installed with an identity recognition device, which includes a guide rail ID consisting of the ID numbers of the wireless labels sequentially arranged and summarized.Type: GrantFiled: May 9, 2023Date of Patent: April 16, 2024Assignee: HANSHOW TECHNOLOGY CO., LTD.Inventors: Shiguo Hou, Jianguo Zhao, Min Liang, Le Zhuo, Sheng Yi, Yang Zhao, Yanwei Wang, Linjiang Wang
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Patent number: 11961998Abstract: Provided is a method of producing multiple particulates, the method comprising: (a) dispersing multiple primary particles of an anode active material, having a particle size from 2 nm to 20 ?m, and particles of a polymer foam material, having a particle size from 50 nm to 20 ?m, and an optional adhesive or binder in a liquid medium to form a slurry; and (b) shaping the slurry and removing the liquid medium to form the multiple particulates having a diameter from 100 nm to 50 ?m; wherein at least one of the multiple particulates comprises a polymer foam material having pores and a single or a plurality of the primary particles embedded in or in contact with the polymer foam material, wherein the primary particles have a total solid volume Va, and the pores have a total pore volume Vp, and the volume ratio Vp/Va is from 0.1/1.0 to 10/1.Type: GrantFiled: May 6, 2019Date of Patent: April 16, 2024Assignee: Honeycomb Battery CompanyInventors: Yi-Jun Lin, Yen-Po Lin, Sheng-Yi Lu, Bor Z. Jang
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Publication number: 20240114380Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. In certain configurations, the UE establishes a connection supporting an extended reality (XR) application service with a base station. The UE reports, to the base station, a delay status report (DSR) to indicate a buffer size for data to be transmitted to the base station. The DSR includes timing information. The UE receives a configuration instruction from the base station. The UE configures resources on the UE according to the configuration instruction to transmit the data to the base station.Type: ApplicationFiled: September 13, 2023Publication date: April 4, 2024Inventors: Ming-Yuan Cheng, Pradeep Jose, Chia-Chun Hsu, Sheng-Yi Ho
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Publication number: 20240038892Abstract: A semiconductor device includes a transistor disposed in an active region. The transistor comprises a source/drain feature, a fin channel and a gate structure wrapping over the fin channel. The transistor also includes an insulation region disposed at an active edge. The active edge is at a boundary of the active region. The insulation region includes a trench. The trench has a tapered portion. A width of the tapered portion of the trench at a top of the fin channel is greater than a width of the tapered portion of the trench at a bottom of the gate structure.Type: ApplicationFiled: July 29, 2022Publication date: February 1, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ya-Yi Tsai, Sheng-Yi Hsiao, Shu-Yuan Ku, Ryan Chia-Jen Chen
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Patent number: 11868839Abstract: A device detecting system is provided. The device detecting system includes a bar code scanner, a plurality of device accommodating spaces, a screen, and a server. The server obtains bar code information via the bar code scanner and opens one of the device accommodating spaces based on the bar code information to accommodate an electronic device. The server performs a test procedure on the electronic device to generate a test result, and displays the test result and operation information corresponding to the test result on the screen.Type: GrantFiled: May 5, 2022Date of Patent: January 9, 2024Assignee: ASUSTEK COMPUTER INC.Inventors: Chien-Chih Chang, Pei-Yin Chen, Wei-Han Lin, Bo-Rong Chu, Yen-Ting Liu, Yu-Shen Mai, Kuan-Yu Hsiao, Chia-Hsien Lin, Pei-Yu Liao, Chun-Yen Lai, Sheng-Yi Chen
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Publication number: 20230419111Abstract: The performance of a neural network (NN) and/or deep neural network (DNN) can limited by the number of operations being performed as well as management of data among the various memory components of the NN/DNN. A sparsity-inducing regularization optimization process is performed on a machine learning model to generate a compressed machine learning model. A machine learning model is trained using a first set of training data. A sparsity-inducing regularization optimization process is executed on the machine learning model. Based on the sparsity-inducing regularization optimization process, a compressed machine learning model is received. The compressed machine learning model is executed to generate one or more outputs.Type: ApplicationFiled: August 30, 2023Publication date: December 28, 2023Applicant: Microsoft Technology Licensing, LLCInventors: Tianyi CHEN, Sheng YI, Yixin SHI, Xiao TU
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Publication number: 20230402544Abstract: A FinFET includes a semiconductor substrate, a semiconductor fin, a gate structure, and an isolation structure. The semiconductor fin protrudes from the semiconductor substrate. The gate structure is disposed across a first segment of the semiconductor fin. The isolation structure interrupts a continuity of a second segment of the semiconductor fin. The isolation structure has a first portion and a second portion stacked on the first portion. Sidewalls of the first portion are inclined and sidewalls of the second portion are straight. A top surface of the first portion is coplanar with a top surface of the gate structure.Type: ApplicationFiled: June 13, 2022Publication date: December 14, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ya-Yi Tsai, Sheng-Yi Hsiao, Chao-Hsuan Chen, Yun-Ting Chiang, Shu-Yuan Ku
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Publication number: 20230402455Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a fin disposed over a semiconductor substrate, and the fin has a first width. The structure further includes an isolation region disposed around the fin, a gate electrode disposed over the fin and the isolation region, and a fill material disposed in the gate electrode. The fill material is in contact with a top surface of a portion of the semiconductor substrate, the top surface has at least a portion having a substantially flat cross-section, and the portion of the top surface has a second width substantially greater than the first width.Type: ApplicationFiled: January 15, 2023Publication date: December 14, 2023Inventors: Ya-Yi TSAI, Sheng-Yi Hsiao, Shu-Yuan KU, Ryan Chia-Jen CHEN, Tzu-Ging LIN, Jih-Jse LIN, Yih-Ann LIN