Abstract: A serial-parallel interface circuit with nonvolatile memories is provided. A control module generates a plurality of control signals, wherein the control signals include readout and write-in control signals and memory programming control signals. An input terminal receives a plurality of digital data from external. The digital data are transmitted to the input terminal serially. Memory modules are coupled to the input terminal and receive the control signals from the control module. The input terminal transmits the digital data to the memory modules. One of the memory modules includes a memory unit, and the memory unit stores or transmits one bit of the digital data based on a high voltage control signal and a memory control signal. A plurality of output signal lines are respectively coupled to the memory modules. The memory unit transmits the one bit of the digital data to one of the output signal lines.

Abstract: An operational transconductance amplifier includes a fully-differential amplifying circuit, a bias driving circuit, and a common mode feedback circuit. The fully-differential amplifying circuit is configured for receiving a differential input voltage and providing a differential output voltage. The fully-differential amplifying circuit includes a plurality of diffusor-differential-pair circuits. The bias driving circuit is configured for providing at least one first bias current to drive the fully-differential amplifying circuit and adjust the transconductance of the transconductance amplifier. The common mode feedback circuit is configured for stabilizing the differential output voltage. An operational transconductance amplifier-capacitor (OTA-C) filter and a high order filter are disclosed herein as well.

Abstract: An operational transconductance amplifier includes a cascode differential-pair amplifying circuit, a bias driving circuit, and a common mode feedback circuit. The cascode differential-pair amplifying circuit is configured for receiving a differential input voltage and for providing a differential output voltage. The bias driving circuit is configured for providing a first bias current to drive the cascode differential-pair amplifying circuit and for adjusting the transconductance of the transconductance amplifier. The bias driving circuit includes a first floating-gate transistor. The first floating-gate transistor is configured for adjusting the first bias current. The common mode feedback circuit is configured for adjusting a second bias current of the cascode differential-pair amplifying circuit according to the differential output voltage so that the differential output voltage is stabilized.

Abstract: A signal receiver may comprise circuitry for applying multi-level sampling to an input signal, using a plurality of sampling rates that comprises at least two different sampling rates, and circuitry for processing one or more outputs of the multi-level sampling. The processing may comprises sampling at a sampling rate that is different than each of the plurality of sampling rates used during the multi-level sampling and applying analog-to-digital conversion. At least one of the sampling rates used during the multi-level sampling and/or the sampling rate used during the processing may be set based on configuring of one or more clock signals used during the multi-level sampling and/or during the processing. At least one of the one or more clock signals may be configured based on reduction of frequency of a corresponding base clock signal.

Abstract: A dielectric constant measurement circuit includes a dielectric constant sensor, an oscillator controlling circuit, a waveform converting circuit, and a counting readout circuit. The oscillator controlling circuit generates an oscillation waveform according to the response of the dielectric constant sensor to a dielectric material. The waveform converting circuit converts the oscillation waveform into frequency division square waves. The counting readout circuit includes a switching counter, a switching circuit, a reference current source, and a current integrator.

Abstract: A serial-parallel interface circuit with nonvolatile memories is provided. A control module generates a plurality of control signals, wherein the control signals include readout and write-in control signals and memory programming control signals. An input terminal receives a plurality of digital data from external. The digital data are transmitted to the input terminal serially. Memory modules are coupled to the input terminal and receive the control signals from the control module. The input terminal transmits the digital data to the memory modules. One of the memory modules includes a memory unit, and the memory unit stores or transmits one bit of the digital data based on a high voltage control signal and a memory control signal. A plurality of output signal lines are respectively coupled to the memory modules. The memory unit transmits the one bit of the digital data to one of the output signal lines.

Abstract: A signal receiver may comprise a first sampling circuitry that is operable to sample in a first level at a particular main sampling rate; a second sampling circuitry that is operable to sample in a second level, an output of the first sampling circuitry, at a second sampling rate that is reduced compared to the main sampling rate; a third sampling circuitry that is operable to sample in a third level, one or more outputs of the second sampling circuitry, at a third sampling rate that is reduced compared to the second sampling rate; and an analog-to-digital conversion (ADC) circuitry for applying analog-to-digital conversion to one or more outputs of the third sampling circuitry.

Abstract: A signal receiver may comprise a first sampling circuitry that is operable to sample in a first level at a particular main sampling rate; a second sampling circuitry that is operable to sample in a second level, an output of the first sampling circuitry, at a second sampling rate that is reduced compared to the main sampling rate; a third sampling circuitry that is operable to sample in a third level, one or more outputs of the second sampling circuitry, at a third sampling rate that is reduced compared to the second sampling rate; and an analog-to-digital conversion (ADC) circuitry for applying analog-to-digital conversion to one or more outputs of the third sampling circuitry.

Abstract: The present invention describes systems and methods to provide programmable analog classifiers. An exemplary embodiment of the present invention provides an analog classifier circuit comprising a bump circuit enabled to store a template vector, wherein the template vector can model a probability distribution with exponential behavior. Furthermore, the bump circuit is enabled to generate an output corresponding to a comparison between an input vector received by the bump circuit and the template vector stored by the bump circuit. Additionally, the analog classifier circuit includes a variable gain amplifier in communication with the bump circuit, and the variable gain amplifier can be adjusted to modify the variance of the template vector.

Abstract: A radio frequency (RF) receiver may comprise a first sampling module that is operable to sample in a first level at a particular main sampling rate; a plurality of second-level sampling modules, wherein each of the plurality of second-level sampling modules is operable to sample in a second level, an output of the first level, at a second sampling rate that is reduced compared to the main sampling rate; and a plurality of third-level modules, each comprising a plurality of third-stage sampling sub-modules that are operable to sample at a third sampling rate that is reduced compared to the second sampling rate, and a plurality of corresponding analog-to-digital conversion (ADC) sub-modules.

Abstract: A system includes a plurality of inputs each configured to receive a filtered version of a source signal. The system extracts the energy information from each input signal and compares the energy information of a plurality of input signals. Alternatively, the system extracts energy information from a signal that is the difference of two input signals. Based on the energy information, the system determines at least one parameter that may be changed in at least one circuit in a plurality of circuits to minimize the differences in energy of the input signals or to minimize the energy of the difference signal. Parameters may include for example amplification, delay, and corner frequency values. The set of circuits may include microphone interface circuits. Merely by way of example, a system with microphone interface circuits may be included in a hearing enhancement device or in a hands-free earpiece.

Abstract: A radio frequency (RF) receiver may comprise a first sampling module that is operable to sample in a first level at a particular main sampling rate; a plurality of second-level sampling modules, wherein each of the plurality of second-level sampling modules is operable to sample in a second level, an output of the first level, at a second sampling rate that is reduced compared to the main sampling rate; and a plurality of third-level modules, each comprising a plurality of third-stage sampling sub-modules that are operable to sample at a third sampling rate that is reduced compared to the second sampling rate, and a plurality of corresponding analog-to-digital conversion (ADC) sub-modules.

Abstract: A system includes a plurality of inputs each configured to receive a filtered version of a source signal. The system extracts the energy information from each input signal and compares the energy information of a plurality of input signals. Alternatively, the system extracts energy information from a signal that is the difference of two input signals. Based on the energy information, the system determines at least one parameter that may be changed in at least one circuit in a plurality of circuits to minimize the differences in energy of the input signals or to minimize the energy of the difference signal. Parameters may include for example amplification, delay, and corner frequency values. The set of circuits may include microphone interface circuits. Merely by way of example, a system with microphone interface circuits may be included in a hearing enhancement device or in a hands-free earpiece.

Abstract: The present invention describes systems and methods to provide programmable analog classifiers. An exemplary embodiment of the present invention provides an analog classifier circuit comprising a bump circuit enabled to store a template vector, wherein the template vector can model a probability distribution with exponential behavior. Furthermore, the bump circuit is enabled to generate an output corresponding to a comparison between an input vector received by the bump circuit and the template vector stored by the bump circuit. Additionally, the analog classifier circuit includes a variable gain amplifier in communication with the bump circuit, and the variable gain amplifier can be adjusted to modify the variance of the template vector.

Abstract: The present invention relates to systems and methods for sensing capacitance change of a capacitive sensor and for optimizing a capacitive sensing circuit. In an exemplary embodiment, a capacitive sensor may be coupled to an amplifier at floating node. A programming circuit is connected to the floating node for controlling a charge on the floating node. A method of controlling the charge of the floating node is also provided. The method includes applying a first predetermined voltage to a source of a programming transistor, applying a second predetermined voltage to a floating gate of the programming transistor, and applying a third predetermined voltage to a drain of the programming transistor until a charge on the floating gate of the programming transistor reaches a predetermined value. The charge on the floating gate of the programming transistor drives the charge on the floating node to the predetermined value, and thus is controlled.

Abstract: The present invention relates to systems and methods for sensing capacitance change of a capacitive sensor and for optimizing a capacitive sensing circuit. In an exemplary embodiment, a capacitive sensor may be coupled to an amplifier at floating node. A programming circuit is connected to the floating node for controlling a charge on the floating node. A method of controlling the charge of the floating node is also provided. The method includes applying a first predetermined voltage to a source of a programming transistor, applying a second predetermined voltage to a floating gate of the programming transistor, and applying a third predetermined voltage to a drain of the programming transistor until a charge on the floating gate of the programming transistor reaches a predetermined value. The charge on the floating gate of the programming transistor drives the charge on the floating node to the predetermined value, and thus is controlled.