Abstract: A method for fabricating a semiconductor device includes the steps of first forming a shallow trench isolation (STI) in a substrate, forming a first gate structure on the substrate and adjacent to the STI, forming a first doped region between the first gate structure and the STI, forming a second doped region between the first doped region and the first gate structure, forming a first contact plug on the first doped region, and then forming a second contact plug on the second doped region.

Abstract: In some embodiments, the present disclosure relates to a wafer edge trimming apparatus that includes a processing chamber defined by chamber housing. Within the processing chamber is a wafer chuck configured to hold onto a wafer structure. Further, a blade is arranged near an edge of the wafer chuck and configured to remove an edge potion of the wafer structure and to define a new sidewall of the wafer structure. A laser sensor apparatus is configured to direct a laser beam directed toward a top surface of the wafer chuck. The laser sensor apparatus is configured to measure a parameter of an analysis area of the wafer structure. Control circuitry is to the laser sensor apparatus and the blade. The control circuitry is configured to start a damage prevention process when the parameter deviates from a predetermined threshold value by at least a predetermined shift value.

Abstract: An LED driving device with an adjustable dimming depth is provided. The LED driving device includes an LED driver and a dimming depth control circuit. The LED driver includes a dimming control circuit and a driving circuit. The dimming control circuit generates a first pulse-width modulation (PWM) signal according to a first brightness indication signal. The driving circuit drives a first light source and adjusts a brightness of the first light source. A duty ratio of the first PWM signal and the first driving current have a first relationship therebetween. The dimming depth control circuit includes a first variable resistance circuit, and the first variable resistance circuit controls a magnitude of a first variable resistance between a first current sampling terminal and a ground terminal according to a first dimming depth control signal. The first relationship defines a first dimming depth that varies with the first variable resistance.

Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

Abstract: The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a first interconnect layer and a second interconnect layer. The first interconnect layer is disposed on the substrate, and the first interconnect layer includes a first dielectric layer around a plurality of first magnetic tunneling junction (MTJ) structures. The second interconnect layer is disposed on the first interconnect layer, and the second interconnect layer includes a second dielectric layer around a plurality of second MTJ structures, wherein, the second MTJ structures and the first MTJ structures are alternately arranged along a direction. The semiconductor device may obtain a reduced size of each bit cell under a permissible process window, so as to improve the integration of components.

Abstract: A connect structure for semiconductor processing equipment includes a housing configured to mate a deformable pipe with a non-deformable pipe. The housing includes a first annular sidewall to receive the deformable pipe and a second annular sidewall defining a first thread structure. An annular bead is connected to the first annular sidewall to flexibly deform the deformable pipe toward the non-deformable pipe structure when the first thread structure rotatably engages a second thread structure of the non-deformable pipe.

Abstract: A bonding tool includes a gas supply line that may extend directly between valves associated with one or more gas supply tanks and a processing chamber such that gas supply line is uninterrupted without any intervening valves or other types of structures that might otherwise cause a pressure buildup in the gas supply line between the processing chamber and the valves associated with the one or more gas supply tanks. The pressure in the gas supply line may be maintained at or near the pressure in the processing chamber so that gas provided to the processing chamber through the gas supply line does not cause a pressure imbalance in the processing chamber, which might otherwise cause early or premature contact between semiconductor substrates that are to be bonded in the processing chamber.

Abstract: An image processing system and a processing method of video stream are provided. The first image is obtained according to a parameter. The deformation correction procedure is performed on the first image, and the second image is generated. The identification detection procedure is performed on the second image, and a detected result is generated. Control information is generated according to the detected result. The parameter is adjusted according to the control information, and a third image is generated. The second image and the third image are output. Therefore, the subsequent application could be enhanced through the dual image outputs.

Abstract: The present disclosure relates to exclusion rings for use in processing a semiconductor substrate in a processing chamber, such as a chemical vapor deposition chamber. The exclusion ring includes an alignment structure that cooperates with an alignment structure on a platen on which the exclusion ring will rest during processing of the wafer. The first alignment structure includes a guiding surface which promotes the reception of and positioning of the second alignment structure within the first alignment structure. Methods of utilizing the described exclusion rings are also described.

Abstract: The present disclosure is directed to a transfer blade including a first end segment, a second end segment opposite to the first end segment, and an intermediate segment extending from the first end segment to the second end segment. The first end segment includes a first contact region and the second end segment includes a second contact region. The first and second contact regions are configured to contact locations of a surface of a workpiece that do not overlap or are not aligned with a sensitive area of the workpiece. The sensitive area of the workpiece may be an EUV frame or a reticle of the workpiece. A non-contact region extends continuously along the first end segment, the intermediate segment, and the second end segment, and the non-contact region overlaps the sensitive area of the workpiece and is spaced apart from the sensitive area of the workpiece.

Abstract: The present disclosure is directed to workpiece support for supporting a workpiece during semiconductor processing. The workpiece support includes one or more support frame bodies including a plurality of spaced apart spacers on a first surface of the support frame bodies. The spacers include a first surface spaced apart from the first surface of the support frame body. The spacing between the first surface of the spacers and the first surface of the support frame body results in the underside of the workpiece contacting the spacers but not contacting the first surface of the support frame body. Portions of the underside of the workpiece that do not contact the first surface of the support frame body are less susceptible to damage or accumulation of unwanted debris.

Abstract: A photomask assembly may be formed such that stress relief trenches are formed in a pellicle frame of the photomask assembly. The stress relief trenches may reduce or prevent damage to a pellicle that may otherwise result from deformation of the pellicle. The stress relief trenches may be formed in areas of the pellicle frame to allow the pellicle frame to deform with the pellicle, thereby reducing the amount damage to the pellicle caused by the pellicle frame.

Abstract: A preclean process may be omitted from a eutectic bonding sequence. To remove oxide from one or more surfaces of a device wafer of a micro-electromechanical-system (MEMS) structure, a duration of an acid-based etch process in the eutectic bonding sequence may be increased relative to the duration of the acid-based etch process when the preclean process is performed. The increased duration of the acid-based etch process enables the acid-based etch process to remove the oxide from the one or more surfaces of the device wafer without the use of a preceding preclean process. This reduces the complexity and cycle time of the eutectic bonding sequence, reduces the risk of stiction between suspended mechanical components of the MEMS structure, and/or reduces the likelihood that the MEMS structure may be rendered defective or inoperable during manufacturing, which increases process yield.

Abstract: A photomask assembly may be formed such that stress relief trenches are formed in a pellicle frame of the photomask assembly. The stress relief trenches may reduce or prevent damage to a pellicle that may otherwise result from deformation of the pellicle. The stress relief trenches may be formed in areas of the pellicle frame to allow the pellicle frame to deform with the pellicle, thereby reducing the amount damage to the pellicle caused by the pellicle frame.

Abstract: A wafer pod transfer assembly includes a wafer pod port to receive a wafer pod, a transfer axle coupled to the wafer pod port, a shaft receiver, a shaft coupled to the transfer axle and to the shaft receiver, a pin through the shaft receiver and through the shaft, wherein the pin comprises a first end and a second end, opposite the first end, and a pin buckle including a first loop and a second loop. The pin buckle is coupled to the pin, the first loop encircles the first end of the pin, and the second loop encircles the second end of the pin.

Abstract: A preclean process may be omitted from a eutectic bonding sequence. To remove oxide from one or more surfaces of a device wafer of a micro-electromechanical-system (MEMS) structure, a duration of an acid-based etch process in the eutectic bonding sequence may be increased relative to the duration of the acid-based etch process when the preclean process is performed. The increased duration of the acid-based etch process enables the acid-based etch process to remove the oxide from the one or more surfaces of the device wafer without the use of a preceding preclean process. This reduces the complexity and cycle time of the eutectic bonding sequence, reduces the risk of stiction between suspended mechanical components of the MEMS structure, and/or reduces the likelihood that the MEMS structure may be rendered defective or inoperable during manufacturing, which increases process yield.

Abstract: A wafer pod transfer assembly includes a wafer pod port to receive a wafer pod, a transfer axle coupled to the wafer pod port, a shaft receiver, a shaft coupled to the transfer axle and to the shaft receiver, a pin through the shaft receiver and through the shaft, wherein the pin comprises a first end and a second end, opposite the first end, and a pin buckle including a first loop and a second loop. The pin buckle is coupled to the pin, the first loop encircles the first end of the pin, and the second loop encircles the second end of the pin.

Abstract: An apparatus for performing a deposition process on a semiconductor wafer includes a chamber, a wafer holder, and a shielding structure. The chamber contains a reaction area, the wafer holder is disposed in the chamber to hold the semiconductor wafer, and the reaction area is above the semiconductor wafer. The shielding structure is disposed in the chamber and isolates an inner sidewall of the chamber from the reaction area. The shielding structure includes a base member, a first member, and a second member. The base member is disposed between the inner sidewall of the chamber and the wafer holder. The first member is disposed on the base member and is windowless. The second member is disposed on the base member and within the first member, and the second member includes a sidewall provided with a first window to transfer the semiconductor wafer.

Abstract: An image processing system and a processing method of video stream are provided. The first image is obtained according to a parameter. The deformation correction procedure is performed on the first image, and the second image is generated. The identification detection procedure is performed on the second image, and a detected result is generated. Control information is generated according to the detected result. The parameter is adjusted according to the control information, and a third image is generated. The second image and the third image are output. Therefore, the subsequent application could be enhanced through the dual image outputs.