Abstract: A bicycle crank comprises an L-type left crank and an L-type right crank. The L-type left/right cranks are respectively and integrally composed of a crank and a connection head, and includes a through hole passing through the crank and the connection head, a left compression shaft and a right compression shaft respectively disposed to terminals of the through holes of the L-type left/right cranks, a cone shaped member in which two ends are respectively disposed in the left and right compression shafts and the inner surface has screw threads, a rotary sleeve that is a hollow and integrally formed, and two locking members in which a terminal has screw threads corresponding to the cone shaped member and for respectively passing through the through holes and locked to two ends of the cone shaped member to connect the L-type left crank and the L-type right crank.

Abstract: A method of forming a semiconductor device having a through-silicon via (TSV) is provided. A semiconductor device is provided having a first dielectric layer formed thereon. One or more dielectric layers are formed over the first dielectric layer, such that each of the dielectric layers have a stacking structure, wherein the stacking structures in the one or more dielectric layers are vertically aligned. The stacking structures may be, for example, metal rings. The stacking structures are then removed to form a first recess. A second recess is formed by extending the first recess into the substrate. The second recess is filled with a conductive material to form the TSV.

Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Abstract: The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.

Abstract: An integrated circuit structure includes a semiconductor substrate; and an interconnect structure overlying the semiconductor substrate. A solid metal ring is formed in the interconnect structure, with substantially no active circuit being inside the solid metal ring. The integrated circuit structure further includes a through-silicon via (TSV) having a portion encircled by the solid metal ring. The TSV extends through the interconnect structure into the semiconductor substrate.

Abstract: A method of forming a semiconductor device having a through-silicon via (TSV) is provided. A semiconductor device is provided having a first dielectric layer formed thereon. One or more dielectric layers are formed over the first dielectric layer, such that each of the dielectric layers have a stacking structure, wherein the stacking structures in the one or more dielectric layers are vertically aligned. The stacking structures may be, for example, metal rings. The stacking structures are then removed to form a first recess. A second recess is formed by extending the first recess into the substrate. The second recess is filled with a conductive material to form the TSV.

Abstract: A camera module includes an image sensor chip module and a lens module. The image sensor chip module includes a base, an image sensor chip disposed on the base and electrically connected with the base, and a frame disposed on the base and surrounding the image sensor chip therein. The lens module includes a barrel mounted on the frame of the image sensor chip module and at least two lens units disposed in the barrel respectively. One of the lens units is disposed on the frame and over the image sensor chip and has a transparent cover capable of filtering infrared rays out and a lens attached to a side of the transparent cover such that the transparent cover separates the lens away from the image sensor chip.

Abstract: A multi-interface conversion device includes a USB-to-IDE interface bridging unit, an IDE-to-SATA interface bridging unit, an IDE switching unit, and a switching logic unit. The USB-to-IDE interface bridging unit provides USB to IDE bridging and conversion. The IDE-to-SATA interface bridging unit provides IDE to SATA interface conversion or IDE to eSATA interface conversion or SATA to eSATA interface conversion. The IDE-to-SATA interface bridging unit is connected to the USB-to-IDE interface bridging unit to transmit USB-to-IDE converted data to the IDE-to-SATA interface bridging unit to provide conversion between USB interface and SATA. The IDE switching unit is connected to the USB-to-IDE interface bridging unit and the IDE-to-SATA interface bridging unit for switching the output IDE interface and signal between the USB-to-IDE interface bridging unit and the IDE-to-SATA interface bridging unit.

Abstract: A dummy region varactor for improving a CMP process and improving electrical isolation from active areas and a method for forming the same, the varactor including a semiconductor substrate having a dummy region said dummy region including a first well region having a first polarity; shallow trench isolation (STI) structures disposed in the dummy region defining adjacent mesa regions comprising first, second, and third mesa regions; a second well region having a second polarity underlying the first mesa region having the second polarity to form a PN junction interface; wherein said second and third mesa regions having the first polarity are formed adjacent either side of said first mesa region.

Abstract: The present invention discloses an improved bicycle front fork structure, wherein a reinforcement device is integrated with the inner wall of the joint between the front fork and the vertical tube to enhance the structural strength lest the joint be fractured or distorted. Thereby, the safety of riding a bicycle is promoted.

Abstract: The present invention discloses a serial ATA (SATA) card reader control system and a controlling method of the same. The SATA card reader control system and the controlling method are capable of identifying a flash memory card type which is intended to be accessed by an SATA host based on a 4-bit Port Multiplier port information defined in SATA Frame Information Structure (FIS). Accordingly, the SATA host with usage of only one physical transport can access at most fifteen different types of flash memory cards. And a SATA transmission interface can be utilized in a multi-card reader in order to access various types of flash memory cards and increase the transmission speed between the SATA host and the multi-card reader.

Abstract: A bridge device for SATA-interfaced hosts is provided, including a pair of physical units, a pair of link units, a pair of transmission ports, and at least a bridge unit. Each physical unit provides the connection to a SATA-interfaced host. The link unit links the physical unit and the transmission port, and encodes and decodes the transmitted and received data. The transmission port controls the host-to-device connection, registers, and state of the SATA interface. The bridge unit connects between two transmission ports, and so that the two SATA-interfaced hosts can transmit and receive data. The bridge device of the present invention allows the SATA-interfaced hosts to transmit and receive data and signals at a high speed.

Abstract: A multi-interface conversion device includes a USB-to-IDE interface bridging unit, an IDE-to-SATA interface bridging unit, an IDE switching unit, and a switching logic unit. The USB-to-IDE interface bridging unit provides USB to IDE bridging and conversion. The IDE-to-SATA interface bridging unit provides IDE to SATA interface conversion or IDE to eSATA interface conversion or SATA to eSATA interface conversion. The IDE-to-SATA interface bridging unit is connected to the USB-to-IDE interface bridging unit to transmit USB-to-IDE converted data to the IDE-to-SATA interface bridging unit to provide conversion between USB interface and SATA. The IDE switching unit is connected to the USB-to-IDE interface bridging unit and the IDE-to-SATA interface bridging unit for switching the output IDE interface and signal between the USB-to-IDE interface bridging unit and the IDE-to-SATA interface bridging unit.

Abstract: A dummy region varactor for improving a CMP process and improving electrical isolation from active areas and a method for forming the same, the varactor including a semiconductor substrate having a dummy region said dummy region including a first well region having a first polarity; shallow trench isolation (STI) structures disposed in the dummy region defining adjacent mesa regions comprising first, second, and third mesa regions; a second well region having a second polarity underlying the first mesa region having the second polarity to form a PN junction interface; wherein said second and third mesa regions having the first polarity are formed adjacent either side of said first mesa region.

Abstract: A method of forming an NMOS device with reduced device degradation, generated during a constant current stress, has been developed. The reduced device degradation is attributed to the use of a high temperature oxide (HTO), layer, used as an underlying component of composite insulator spacers, formed on the sides of the NMOS gate structures. After definition of an insulator capped polycide gate structure a thin, (140 to 160 Angstrom), HTO layer is deposited at a temperature between about 700 to 800° C., followed by the deposition of a silicon nitride layer. Definition of the composite insulator layer, comprised with the underlying, HTO, results in NMOS devices with reduced drain current and reduced transconductance values, when compared to counterparts fabricated with composite insulator spacers formed without the thin, HTO layer featured in this invention.

Abstract: A method is provided to prevent the forming of a high de-focusing ledge or step on the back side of a substrate or a semiconductor wafer in order to improve the photolithographic process steps in semiconductor manufacturing. In semiconductor manufacturing, various processes are performed to form various dielectric and metal layers on the front side of wafers. However, some of these materials deposit on the back side of the wafer as well. These unwanted deposits result in contaminants that break off from the back side, causing reliability problems. Those that do stay on, on the other hand, cause irregular topology, thus affecting the focusing of stepper equipment during photolithographic processes. It is disclosed in the present invention a method of forming an oxide layer which prevents the forming of such de-focusing steps on the back side of a wafer.