Patents by Inventor Shenlin Chen
Shenlin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8525241Abstract: An image sensor having a pixel array comprises periphery elements formed over a substrate, an oxide layer formed over the periphery elements, an epitaxial layer formed in an opening in the oxide layer in a pixel array area, and a plurality of photosensitive elements of the pixel array formed in the epitaxial layer. Formation of an initial metallization layer occurs after the formation of the photosensitive elements in the epitaxial layer. The photosensitive elements can thus be formed in the epitaxial layer at a higher level within an image sensor stack than that of the initial metallization layer. This advantageously allows stack height and pixel size to be reduced, and fill factor to be increased. The image sensor may be implemented in a digital camera or other type of digital imaging device.Type: GrantFiled: May 16, 2012Date of Patent: September 3, 2013Assignee: Omni Vision Technologies, Inc.Inventor: Shenlin Chen
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Publication number: 20120229684Abstract: An image sensor having a pixel array comprises periphery elements formed over a substrate, an oxide layer formed over the periphery elements, an epitaxial layer formed in an opening in the oxide layer in a pixel array area, and a plurality of photosensitive elements of the pixel array formed in the epitaxial layer. Formation of an initial metallization layer occurs after the formation of the photosensitive elements in the epitaxial layer. The photosensitive elements can thus be formed in the epitaxial layer at a higher level within an image sensor stack than that of the initial metallization layer. This advantageously allows stack height and pixel size to be reduced, and fill factor to be increased. The image sensor may be implemented in a digital camera or other type of digital imaging device.Type: ApplicationFiled: May 16, 2012Publication date: September 13, 2012Applicant: OMNIVISION TECHNOLOGIES, INC.Inventor: Shenlin Chen
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Patent number: 8211732Abstract: An image sensor having a pixel array comprises periphery elements formed over a substrate, an oxide layer formed over the periphery elements, an epitaxial layer formed in an opening in the oxide layer in a pixel array area, and a plurality of photosensitive elements of the pixel array formed in the epitaxial layer. Formation of an initial metallization layer occurs after the formation of the photosensitive elements in the epitaxial layer. The photosensitive elements can thus be formed in the epitaxial layer at a higher level within an image sensor stack than that of the initial metallization layer. This advantageously allows stack height and pixel size to be reduced, and fill factor to be increased. The image sensor may be implemented in a digital camera or other type of digital imaging device.Type: GrantFiled: September 11, 2008Date of Patent: July 3, 2012Assignee: OmniVision Technologies, Inc.Inventor: Shenlin Chen
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Publication number: 20100059802Abstract: An image sensor having a pixel array comprises periphery elements formed over a substrate, an oxide layer formed over the periphery elements, an epitaxial layer formed in an opening in the oxide layer in a pixel array area, and a plurality of photosensitive elements of the pixel array formed in the epitaxial layer. Formation of an initial metallization layer occurs after the formation of the photosensitive elements in the epitaxial layer. The photosensitive elements can thus be formed in the epitaxial layer at a higher level within an image sensor stack than that of the initial metallization layer. This advantageously allows stack height and pixel size to be reduced, and fill factor to be increased. The image sensor may be implemented in a digital camera or other type of digital imaging device.Type: ApplicationFiled: September 11, 2008Publication date: March 11, 2010Inventor: Shenlin Chen
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Publication number: 20100026824Abstract: An image sensor having a pixel array includes a sensor layer comprising a plurality of photosensitive elements of the pixel array, a circuit layer comprising circuitry associated with the pixel array, and a crosstalk reduction layer arranged between the sensor layer and the circuit layer and configured to reduce crosstalk between adjacent ones of the photosensitive elements. The crosstalk reduction layer may comprise, for example, an amorphous silicon germanium (a-SiGe) layer specifically configured to reduce red light crosstalk in the image sensor. The image sensor may be implemented in a digital camera or other type of digital imaging device.Type: ApplicationFiled: July 29, 2008Publication date: February 4, 2010Inventor: Shenlin Chen
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Publication number: 20100006964Abstract: A backside illuminated image sensor includes a sensor layer comprising a plurality of photosensitive elements of the pixel array, a circuit layer comprising circuitry associated with the pixel array, a conductive layer formed on a backside surface of the sensor layer, and one or more conductive contacts configured to couple the conductive layer to a bias source in the circuit layer. The biased conductive layer produces an electric field across the photosensitive elements of the pixel array that facilitates charge carrier collection and reduces crosstalk between adjacent photosensitive elements, thereby providing improved quantum efficiency in the image sensor. The image sensor may be implemented in a digital camera or other type of digital imaging device.Type: ApplicationFiled: July 10, 2008Publication date: January 14, 2010Inventors: Shenlin Chen, Robert M. Guidash
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Publication number: 20090294819Abstract: Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material.Type: ApplicationFiled: August 10, 2009Publication date: December 3, 2009Inventors: Randhir P.S. Thakur, Garry A. Mercaldi, Michael Nuttall, Shenlin Chen, Er-Xuan Ping
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Patent number: 7528430Abstract: The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the second semiconductor layer, and semiconductor-containing seeds are formed over the third semiconductor layer. The seeds are annealed to form the rugged semiconductor-containing surface. The first, second and third semiconductor layers are part of a common stack, and can be together utilized within a storage node of a capacitor construction. The invention also includes semiconductor structures comprising rugged surfaces. The rugged surfaces can be, for example, rugged silicon.Type: GrantFiled: June 7, 2006Date of Patent: May 5, 2009Assignee: Micron Technology, Inc.Inventors: Shenlin Chen, Trung Tri Doan, Guy T. Blalock, Lyle D. Breiner, Er-Xuan Ping
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Patent number: 7440255Abstract: A capacitor construction includes a first electrode and a layer between the first electrode and a surface supporting the capacitor construction. The capacitor construction can exhibit a lower RC time constant compared to an otherwise identical capacitor construction lacking the layer. Alternatively, or additionally, the first electrode may contain Si and the layer may limit the Si from contributing to formation of metal silicide material between the first electrode and the supporting surface. The layer may be a nitride layer and may be conductive or insulative. When conductive, the layer may exhibit a first conductivity greater than a second conductivity of the first electrode. The capacitor construction may be used in memory devices.Type: GrantFiled: July 21, 2003Date of Patent: October 21, 2008Assignee: Micron Technology, Inc.Inventors: Brent A. McClure, Casey R. Kurth, Shenlin Chen, Debra K. Gould, Lyle D. Breiner, Er-Xuan Ping, Fred D. Fishburn, Hongmei Wang
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Patent number: 7405438Abstract: The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the second semiconductor layer, and semiconductor-containing seeds are formed over the third semiconductor layer. The seeds are annealed to form the rugged semiconductor-containing surface. The first, second and third semiconductor layers are part of a common stack, and can be together utilized within a storage node of a capacitor construction. The invention also includes semiconductor structures comprising rugged surfaces. The rugged surfaces can be, for example, rugged silicon.Type: GrantFiled: September 20, 2004Date of Patent: July 29, 2008Assignee: Micron Technology, Inc.Inventors: Shenlin Chen, Trung Tri Doan, Guy T. Blalock, Lyle D. Breiner, Er-Xuan Ping
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Patent number: 7355232Abstract: A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of hemispherical grained polysilicon (HSG) as part of a dual-sided lower capacitor electrode. Prior to the dielectric formation, the lower capacitor electrode may be optionally annealed to improve capacitance.Type: GrantFiled: September 6, 2005Date of Patent: April 8, 2008Assignee: Micron Technology, Inc.Inventors: Er-Xuan Ping, Shenlin Chen
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Patent number: 7321148Abstract: The invention encompasses a method of forming a rugged silicon-containing surface. A layer comprising amorphous silicon is provided within a reaction chamber at a first temperature. The temperature is increased to a second temperature at least 40° C. higher than the first temperature while flowing at least one hydrogen isotope into the chamber. After the temperature reaches the second temperature, the layer is seeded with seed crystals. The seeded layer is then annealed to form a rugged silicon-containing surface. The rugged silicon-containing surface can be incorporated into a capacitor construction. The capacitor construction can be incorporated into a DRAM cell, and the DRAM cell can be utilized in an electronic system.Type: GrantFiled: August 6, 2004Date of Patent: January 22, 2008Assignee: Micron Technology, Inc.Inventors: Guy T. Blalock, Lyle D. Breiner, Er-Xuan Ping, Shenlin Chen
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Patent number: 7268382Abstract: The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the second semiconductor layer, and semiconductor-containing seeds are formed over the third semiconductor layer. The seeds are annealed to form the rugged semiconductor-containing surface. The first, second and third semiconductor layers are part of a common stack, and can be together utilized within a storage node of a capacitor construction. The invention also includes semiconductor structures comprising rugged surfaces. The rugged surfaces can be, for example, rugged silicon.Type: GrantFiled: June 7, 2006Date of Patent: September 11, 2007Assignee: Micron Technology, Inc.Inventors: Shenlin Chen, Trung Tri Doan, Guy T. Blalock, Lyle D. Breiner, Er-Xuan Ping
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Publication number: 20060275983Abstract: Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material.Type: ApplicationFiled: August 9, 2006Publication date: December 7, 2006Inventors: Randhir Thakur, Garry Mercaldi, Michael Nuttall, Shenlin Chen, Er-Xuan Ping
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Publication number: 20060237763Abstract: The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the second semiconductor layer, and semiconductor-containing seeds are formed over the third semiconductor layer. The seeds are annealed to form the rugged semiconductor-containing surface. The first, second and third semiconductor layers are part of a common stack, and can be together utilized within a storage node of a capacitor construction. The invention also includes semiconductor structures comprising rugged surfaces. The rugged surfaces can be, for example, rugged silicon.Type: ApplicationFiled: June 7, 2006Publication date: October 26, 2006Inventors: Shenlin Chen, Trung Doan, Guy Blalock, Lyle Breiner, Er-Xuan Ping
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Publication number: 20060228857Abstract: The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the second semiconductor layer, and semiconductor-containing seeds are formed over the third semiconductor layer. The seeds are annealed to form the rugged semiconductor-containing surface. The first, second and third semiconductor layers are part of a common stack, and can be together utilized within a storage node of a capacitor construction. The invention also includes semiconductor structures comprising rugged surfaces. The rugged surfaces can be, for example, rugged silicon.Type: ApplicationFiled: June 7, 2006Publication date: October 12, 2006Inventors: Shenlin Chen, Trung Doan, Guy Blalock, Lyle Breiner, Er-Xuan Ping
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Patent number: 7101756Abstract: Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material.Type: GrantFiled: February 18, 2004Date of Patent: September 5, 2006Assignee: Micron Technology, Inc.Inventors: Randhir P. S. Thakur, Garry A. Mercaldi, Michael Nuttall, Shenlin Chen, Er-Xuan Ping
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Patent number: 7071056Abstract: A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of hemispherical grained polysilicon (HSG) as part of a dual-sided lower capacitor electrode. Prior to the dielectric formation, the lower capacitor electrode may be optionally annealed to improve capacitance.Type: GrantFiled: July 21, 2004Date of Patent: July 4, 2006Assignee: Micron Technology, Inc.Inventors: Er-Xuan Ping, Shenlin Chen
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Patent number: 7034353Abstract: Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material.Type: GrantFiled: September 26, 2001Date of Patent: April 25, 2006Assignee: Micron Technology, Inc.Inventors: Randhir P. S. Thakur, Garry A. Mercaldi, Michael Nuttall, Shenlin Chen, Er-Xuan Ping
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Patent number: 7023039Abstract: The invention includes a method of forming a capacitor electrode. A sacrificial material sidewall is provided to extend at least partially around an opening. A first silicon-containing material is formed within the opening to partially fill the opening, and is doped with conductivity-enhancing dopant. A second silicon-containing material is formed within the partially filled opening, and is provided to be less heavily doped with conductivity-enhancing dopant than is the first silicon-containing material. At least some of the second silicon-containing material is converted into hemispherical grain silicon, and at least some of the sacrificial material sidewall is removed. The invention also encompasses methods of forming capacitors and capacitor assemblies incorporating the above-described capacitor electrode. Further, the invention encompasses capacitor assemblies, and capacitor structures.Type: GrantFiled: September 3, 2002Date of Patent: April 4, 2006Assignee: Micron Technology, Inc.Inventors: Shenlin Chen, Er-Xuan Ping