Abstract: One or more computer processors create a user-event localization model for an identified remote audience member in a plurality of identified remote audience members for an event. The one or more computer processors generate a virtual audience member based the identified remote audience member utilizing a trained generated adversarial network and one or more user preferences. The one or more computer processors present the generated virtual audience member in a location associated with the event. The one or more computer processors dynamically adjust a presented virtual audience member responsive to one or more event occurrences utilizing the created user-event localization model.

Abstract: One or more computer processors create a user-event localization model for an identified remote audience member in a plurality of identified remote audience members for an event. The one or more computer processors generate a virtual audience member based the identified remote audience member utilizing a trained generated adversarial network and one or more user preferences. The one or more computer processors present the generated virtual audience member in a location associated with the event. The one or more computer processors dynamically adjust a presented virtual audience member responsive to one or more event occurrences utilizing the created user-event localization model.

Abstract: A collision avoidance and road safety system is applied to a road network comprised of a plurality of road segments for a location to produce real time or dynamic forecasting of collision risk and root causes of the potential collision.

Abstract: A collision avoidance and road safety system is applied to a road network comprised of a plurality of road segments for a location to produce real time or dynamic forecasting of collision risk and root causes of the potential collision.

Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.

Abstract: A method for predicting risks for information technology service contracts includes calculating a probability of occurrence of each target risk in a target contract; constructing clusters of root causes observed in historical contracts similar to the target contract, for each of the clusters, identifying root causes that co-occur with target contract risks by searching each cluster for root causes of similar historical contract risks such that the identified root causes represent additional new contract risks, and calculating the probability of occurrence of each new target risk identified for the target contract based on root causes identified in the similar historical contract risks. Two root causes are in the same cluster if both root causes occur in one or more contracts in the set of historical contracts, where two root causes co-occur if both root causes are in the same cluster.

Abstract: Techniques for forming enhanced electrical connections are provided. In one aspect, a method of forming an electrical connecting device includes the steps of: depositing an elastomeric material on an electrically insulating carrier; and metallizing the elastomeric material so as to form an electrically conductive layer running continuously through a plane of the carrier and along a surface of the elastomeric material.

Abstract: A method for predicting and quantifying risk in information technology (IT) service contracts includes comparing features of a new IT service contract with similar features from one or more previous IT service contracts selected from a plurality of previous IT service contracts to calculate a similarity value between each pair of the new IT service contract and one of the one or more previous IT service contracts, aggregating the similarity values, and using the aggregated similarity values with a prediction model to predict risk factors affecting the new IT service contract and to quantify an impact of each predicted risk factor on an expected gross profit margin.

Abstract: A method for predicting and quantifying risk in information technology (IT) service contracts includes comparing features of a new IT service contract with similar features from one or more previous IT service contracts selected from a plurality of previous IT service contracts to calculate a similarity value between each pair of the new IT service contract and one of the one or more previous IT service contracts, aggregating the similarity values, and using the aggregated similarity values with a prediction model to predict risk factors affecting the new IT service contract and to quantify an impact of each predicted risk factor on an expected gross profit margin.

Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.

Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.

Abstract: The present invention allows for direct chip-to-chip connections using the shortest possible signal path.

Abstract: The present invention allows for direct chip-to-chip connections using the shortest possible signal path.

Abstract: The present invention allows for direct chip-to-chip connections using the shortest possible signal path.

Abstract: A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.

Abstract: A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.

Abstract: Flexible and rigid interposers for use in the semiconductor industry and methods for manufacturing the same are described. Auto-catalytic processes are used to minimize the costs associated with the production of flexible interposers, while increasing the yield and lifetime. Electrical contact regions are easily isolated and the risk of corrosion is reduced because all portions of the interposer are plated at once. Leads projecting from the flexible portion of the interposers accommodate a greater variety of components to be tested. Rigid interposers include a pin projecting from a probe pad affixed to a substrate. The rigidity of the pin penetrates oxides on a contact pad to be tested. Readily available semiconductor materials and processes are used to manufacture the flexible and rigid interposers according to the invention. The flexible and rigid interposers can accommodate pitches down to 25 ?m.

Abstract: A probe structure for an electronic device is provided. In one aspect, the probe structure includes an electrically insulating carrier having one or more contact structures traversing a plane thereof. Each contact structure includes an elastomeric material having an electrically conductive layer running along at least one surface thereof continuously through the plane of the carrier. The probe structure includes one or more other contact structures adapted for connection to a test apparatus.

Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.

Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.