Patents by Inventor Sherif Galal
Sherif Galal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11885836Abstract: Certain aspects of the present disclosure are generally directed to circuitry and techniques for voltage-to-current conversion. For example, certain aspects provide a circuit for signal amplification including a first amplifier; a first transistor, a gate of the first transistor being coupled to an output of the first amplifier and a drain of the first transistor being coupled to an output node of circuit; a first resistive element coupled between a first input node of the circuit and an input of the first amplifier; a second amplifier; a second transistor, a gate of the second transistor being coupled to an output of the second amplifier and a drain of the second transistor being coupled to the output node of circuit; and a second resistive element coupled between a second input node of the circuit and an input of the second amplifier.Type: GrantFiled: December 27, 2022Date of Patent: January 30, 2024Assignee: QUALCOMM IncorporatedInventors: Ramkumar Sivakumar, Jingxue Lu, Sherif Galal, Xinwang Zhang, Kshitij Yadav
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Patent number: 11876493Abstract: A hybrid class-H/predictive class-G switching amplifier architecture and techniques for amplifying a signal (e.g., an audio signal) using such an architecture. One example method of amplification generally includes delaying an input signal to generate a delayed version of the input signal, amplifying the delayed version of the input signal with an amplifier powered by a boost converter, and selectively controlling the boost converter to operate in at least one of a predictive class-G mode or a class-H mode, based on a magnitude of the input signal.Type: GrantFiled: February 4, 2022Date of Patent: January 16, 2024Assignee: QUALCOMM IncorporatedInventors: Subbarao Surendra Chakkirala, Sherif Galal, Earl Schreyer
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Publication number: 20230300524Abstract: Apparatus and techniques for adaptively adjusting an input current limit for a boost converter supplying power to a load, such as an amplifier. An example circuit for supplying power generally includes a boost converter having an output coupled to a load, and logic configured to adaptively adjust an input current limit for the boost converter based on an estimated output power for the boost converter and to apply the input current limit to the boost converter. One example method for supplying power generally includes converting an input voltage to an output voltage with a boost converter, to power a load for the boost converter, adaptively adjusting an input current limit for the boost converter based on an estimated output power for the boost converter, and applying the input current limit to the boost converter during the converting.Type: ApplicationFiled: March 21, 2022Publication date: September 21, 2023Inventors: Subbarao Surendra CHAKKIRALA, Sherif GALAL, Earl SCHREYER
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Publication number: 20230253934Abstract: A hybrid class-H/predictive class-G switching amplifier architecture and techniques for amplifying a signal (e.g., an audio signal) using such an architecture. One example method of amplification generally includes delaying an input signal to generate a delayed version of the input signal, amplifying the delayed version of the input signal with an amplifier powered by a boost converter, and selectively controlling the boost converter to operate in at least one of a predictive class-G mode or a class-H mode, based on a magnitude of the input signal.Type: ApplicationFiled: February 4, 2022Publication date: August 10, 2023Inventors: Subbarao Surendra CHAKKIRALA, Sherif GALAL, Earl SCHREYER
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Publication number: 20230238925Abstract: Aspects of the present disclosure relate to apparatus and methods for dynamically adjusting the common-mode input signal of a power amplifier, such as a class-D power amplifier. One example power amplifier circuit generally includes a first amplifier having a signal input and a power input; and a common-mode adjustment circuit having a first input coupled to the power input of the first amplifier, having an output coupled to the signal input of the first amplifier, and being configured to generate a common-mode signal to apply to the signal input of the first amplifier, based on a power supply voltage on the power input of the first amplifier.Type: ApplicationFiled: January 26, 2022Publication date: July 27, 2023Inventors: Dongyang TANG, Xinwang ZHANG, ChienChung YANG, Earl SCHREYER, Sherif GALAL
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Patent number: 11683015Abstract: A class-D amplifier including a pulse width modulator including an input configured to receive a first signal based on an input signal, and an output configured to generate a pulse width modulated (PWM) signal; an H-bridge including an input coupled to an output of the pulse width modulator and an output coupled to a load, wherein the H-bridge is configured to generate an output signal across the load based on the PWM signal; and a deadtime compensation circuit coupled to the H-bridge, wherein the deadtime compensation circuit is configured to compensate for deadtime distortion in the output signal. The deadtime compensation circuit may be a feedback circuit between an output of the H-bridge and an input of the pulse width modulator, a pulse modification circuit at the output of the pulse width modulator, or an offset signal generating circuit providing an offset signal to the pulse width modulator.Type: GrantFiled: August 17, 2021Date of Patent: June 20, 2023Assignee: QUALCOMM IncorporatedInventors: ChienChung Yang, Dongyang Tang, Sherif Galal, Xinwang Zhang, Subbarao Surendra Chakkirala, Pradeep Silva
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Publication number: 20230137935Abstract: Certain aspects of the present disclosure are generally directed to circuitry and techniques for voltage-to-current conversion. For example, certain aspects provide a circuit for signal amplification including a first amplifier; a first transistor, a gate of the first transistor being coupled to an output of the first amplifier and a drain of the first transistor being coupled to an output node of circuit; a first resistive element coupled between a first input node of the circuit and an input of the first amplifier; a second amplifier; a second transistor, a gate of the second transistor being coupled to an output of the second amplifier and a drain of the second transistor being coupled to the output node of circuit; and a second resistive element coupled between a second input node of the circuit and an input of the second amplifier.Type: ApplicationFiled: December 27, 2022Publication date: May 4, 2023Inventors: Ramkumar SIVAKUMAR, Jingxue LU, Sherif GALAL, Xinwang ZHANG, Kshitij YADAV
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Publication number: 20230108378Abstract: A method includes receiving first data associated with a first power amplifier and second data associated with a second power amplifier. The method also includes generating a first amplitude limiting signal having gain parameters that are based on the first data and the second data. The first data includes at least one of a temperature measurement associated with the first power amplifier, a supply voltage measurement associated with the first power amplifier, a load resistance associated with the first power amplifier, or a gain associated with the first power amplifier. The method further includes modifying an audio signal based at least in part on the first amplitude limiting signal to generate a first gain-adjusted audio signal. The method also includes providing a first output audio signal to the first power amplifier for amplification. The first output audio signal is based at least in part on the first gain-adjusted audio signal.Type: ApplicationFiled: September 21, 2021Publication date: April 6, 2023Inventors: Earl Schreyer, Sherif Galal, Sang-Uk Ryu, Hui-ya Liao Nelson, Subbarao Surendra Chakkirala, Shreyas Srikanth Payal
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Publication number: 20230058434Abstract: A class-D amplifier including a pulse width modulator including an input configured to receive a first signal based on an input signal, and an output configured to generate a pulse width modulated (PWM) signal; an H-bridge including an input coupled to an output of the pulse width modulator and an output coupled to a load, wherein the H-bridge is configured to generate an output signal across the load based on the PWM signal; and a deadtime compensation circuit coupled to the H-bridge, wherein the deadtime compensation circuit is configured to compensate for deadtime distortion in the output signal. The deadtime compensation circuit may be a feedback circuit between an output of the H-bridge and an input of the pulse width modulator, a pulse modification circuit at the output of the pulse width modulator, or an offset signal generating circuit providing an offset signal to the pulse width modulator.Type: ApplicationFiled: August 17, 2021Publication date: February 23, 2023Inventors: ChienChung YANG, Dongyang TANG, Sherif GALAL, Xinwang ZHANG, Subbarao Surendra CHAKKIRALA, Pradeep SILVA
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Patent number: 11536749Abstract: Certain aspects of the present disclosure are generally directed to circuitry and techniques for voltage-to-current conversion. For example, certain aspects provide a circuit for signal amplification including a first amplifier; a first transistor, a gate of the first transistor being coupled to an output of the first amplifier and a drain of the first transistor being coupled to an output node of circuit; a first resistive element coupled between a first input node of the circuit and an input of the first amplifier; a second amplifier; a second transistor, a gate of the second transistor being coupled to an output of the second amplifier and a drain of the second transistor being coupled to the output node of circuit; and a second resistive element coupled between a second input node of the circuit and an input of the second amplifier.Type: GrantFiled: January 21, 2021Date of Patent: December 27, 2022Assignee: QUALCOMM IncorporatedInventors: Ramkumar Sivakumar, Jingxue Lu, Sherif Galal, Xinwang Zhang, Kshitij Yadav
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Publication number: 20220302884Abstract: Certain aspects of the present disclosure are generally directed to circuitry and techniques for current sensing. For example, certain aspects provide a circuit for signal amplification including a first amplifier, a second amplifier, and a third amplifier. The circuit also includes a first capacitive element coupled between a first output of the first amplifier and a first input of the third amplifier, a second capacitive element coupled between a second output of the first amplifier and a second input of the third amplifier, a third capacitive element coupled between a first output of the second amplifier and the first input of the third amplifier, and a fourth capacitive element coupled between a second output of the second amplifier and the second input of the third amplifier.Type: ApplicationFiled: June 3, 2022Publication date: September 22, 2022Inventors: Khaled Mahmoud ABDELFATTAH ALY, Sherif GALAL, Xin FAN
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Patent number: 11424672Abstract: Certain aspects of the present disclosure provide a power supply circuit. The power supply circuit generally includes: a switched-mode power supply (SMPS) having an inductive element and a first switch coupled to the inductive element; a feedback path coupled between an output of the SMPS and a control input of the first switch; and a current limit circuit comprising a first capacitive element, a charge circuit coupled to the first capacitive element, a first current source, a first resistive element coupled to the first current source, the capacitive element being coupled to a node between the resistive element and the first current source, a sample-and-hold circuit coupled to the first capacitive element, and a clamp circuit coupled between the sample-and-hold circuit and the feedback path.Type: GrantFiled: January 26, 2021Date of Patent: August 23, 2022Assignee: QUALCOMM IncorporatedInventors: Pradeep Silva, Subbarao Surendra Chakkirala, Sherif Galal
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Publication number: 20220239226Abstract: Certain aspects of the present disclosure are directed to an apparatus for voltage regulation. The apparatus generally includes a first switch, an inductive element, the first switch being coupled between a first voltage rail and a first terminal of the inductive element, a second switch coupled between a second voltage rail and the first terminal of the inductive element, a third switch coupled between a second terminal of the inductive element and a reference potential node, and a fourth switch coupled between the second terminal of the inductive element and an output node.Type: ApplicationFiled: January 28, 2021Publication date: July 28, 2022Inventors: Subbarao Surendra CHAKKIRALA, Sherif GALAL, Guoqing MIAO
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Patent number: 11374542Abstract: Certain aspects of the present disclosure are generally directed to circuitry and techniques for current sensing. For example, certain aspects provide a circuit for signal amplification including a first amplifier, a second amplifier, and a third amplifier. The circuit also includes a first capacitive element coupled between a first output of the first amplifier and a first input of the third amplifier, a second capacitive element coupled between a second output of the first amplifier and a second input of the third amplifier, a third capacitive element coupled between a first output of the second amplifier and the first input of the third amplifier, and a fourth capacitive element coupled between a second output of the second amplifier and the second input of the third amplifier.Type: GrantFiled: February 24, 2020Date of Patent: June 28, 2022Assignee: QUALCOMM IncorporatedInventors: Khaled Mahmoud Abdelfattah Aly, Sherif Galal, Xin Fan
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Patent number: 11307604Abstract: In certain aspects, a clamp circuit includes a first current mirror having a first branch and a second branch, wherein the first current mirror is configured to mirror a current flowing through the first branch of the first current mirror to the second branch of the first current mirror. The clamp circuit also includes a second current mirror having a first branch and a second branch, wherein the second current mirror is configured to mirror a current flowing through the first branch of the second current mirror to the second branch of the second current mirror. The first branch of the first current mirror is coupled in series with the second branch of the second current mirror, and the second branch of the first current mirror is coupled in series with the first branch of the second current mirror.Type: GrantFiled: January 7, 2021Date of Patent: April 19, 2022Assignee: QUALCOMM IncorporatedInventors: Kshitij Yadav, Sherif Galal
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Patent number: 11133792Abstract: A level shifter includes a compact bias generator. The compact bias generator generates a first bias signal and a second bias signal, in the absence of a buffer. The level shifter also includes a first latch in a first stage to translate a first voltage to a second voltage based on the first bias signal. The level shifter further includes a second latch in a second stage to translate the first voltage to a third voltage based on the second bias signal. The first bias signal is independent of the second bias signal.Type: GrantFiled: May 27, 2020Date of Patent: September 28, 2021Assignee: QUALCOMM IncorporatedInventors: Qubo Zhou, Sherif Galal
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Publication number: 20210265958Abstract: Certain aspects of the present disclosure are generally directed to circuitry and techniques for current sensing. For example, certain aspects provide a circuit for signal amplification including a first amplifier, a second amplifier, and a third amplifier. The circuit also includes a first capacitive element coupled between a first output of the first amplifier and a first input of the third amplifier, a second capacitive element coupled between a second output of the first amplifier and a second input of the third amplifier, a third capacitive element coupled between a first output of the second amplifier and the first input of the third amplifier, and a fourth capacitive element coupled between a second output of the second amplifier and the second input of the third amplifier.Type: ApplicationFiled: February 24, 2020Publication date: August 26, 2021Inventors: Khaled Mahmoud ABDELFATTAH ALY, Sherif GALAL, Xin FAN
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Publication number: 20210232169Abstract: In certain aspects, a clamp circuit includes a first current mirror having a first branch and a second branch, wherein the first current mirror is configured to mirror a current flowing through the first branch of the first current mirror to the second branch of the first current mirror. The clamp circuit also includes a second current mirror having a first branch and a second branch, wherein the second current mirror is configured to mirror a current flowing through the first branch of the second current mirror to the second branch of the second current mirror. The first branch of the first current mirror is coupled in series with the second branch of the second current mirror, and the second branch of the first current mirror is coupled in series with the first branch of the second current mirror.Type: ApplicationFiled: January 7, 2021Publication date: July 29, 2021Inventors: Kshitij YADAV, Sherif GALAL
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Publication number: 20210234457Abstract: Certain aspects of the present disclosure provide a power supply circuit. The power supply circuit generally includes: a switched-mode power supply (SMPS) having an inductive element and a first switch coupled to the inductive element; a feedback path coupled between an output of the SMPS and a control input of the first switch; and a current limit circuit comprising a first capacitive element, a charge circuit coupled to the first capacitive element, a first current source, a first resistive element coupled to the first current source, the capacitive element being coupled to a node between the resistive element and the first current source, a sample-and-hold circuit coupled to the first capacitive element, and a clamp circuit coupled between the sample-and-hold circuit and the feedback path.Type: ApplicationFiled: January 26, 2021Publication date: July 29, 2021Inventors: Pradeep SILVA, Subbarao Surendra CHAKKIRALA, Sherif GALAL
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Publication number: 20210231710Abstract: Certain aspects of the present disclosure are generally directed to circuitry and techniques for voltage-to-current conversion. For example, certain aspects provide a circuit for signal amplification including a first amplifier; a first transistor, a gate of the first transistor being coupled to an output of the first amplifier and a drain of the first transistor being coupled to an output node of circuit; a first resistive element coupled between a first input node of the circuit and an input of the first amplifier; a second amplifier; a second transistor, a gate of the second transistor being coupled to an output of the second amplifier and a drain of the second transistor being coupled to the output node of circuit; and a second resistive element coupled between a second input node of the circuit and an input of the second amplifier.Type: ApplicationFiled: January 21, 2021Publication date: July 29, 2021Inventors: Ramkumar SIVAKUMAR, Jingxue LU, Sherif GALAL, Xinwang ZHANG, Kshitij YADAV