Patents by Inventor Sherry F. Lee
Sherry F. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150270181Abstract: Product ICs/wafers include additional diagnostic, test, or monitoring structures opportunistically placed in filler cell positions, within tap cells, within decap cells, within scribe line areas, and/or within dummy fill regions. Improved fabrication processes utilize data from such structure(s) in wafer disposition decisions, rework decisions, process control, yield learning, or fault diagnosis.Type: ApplicationFiled: February 3, 2015Publication date: September 24, 2015Inventors: Indranil De, Dennis J. Ciplickas, Stephen Lam, Jonathan Haigh, Vyacheslav V. Rovner, Christopher Hess, Tomasz W. Brozek, Andrzej J. Strojwas, Kelvin Doong, John K. Kibarian, Sherry F. Lee, Kimon W. Michaels, Marcin A. Strojwas, Conor O'Sullivan, Mehul Jain
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Patent number: 7739065Abstract: Methods for determining customized defect detection inspection plans are provided. One method includes fabricating a test chip and generating test chip data from the fabricated test chip. Then, defining systematic signatures from the generated test chip data and identifying a yield relevant systematic signature from the defined systematic signatures. The method includes identifying a layout pattern associated with the yield relevant systematic signature and locating the identified layout pattern on a process module layer of a product chip. Further, the method includes defining a customized defect detection inspection or metrology methodology for detecting systematic defects on the process module layer based on the identified layout pattern associated with the yield relevant systematic signature.Type: GrantFiled: June 12, 2007Date of Patent: June 15, 2010Assignee: PDF Solutions, IncorporatedInventors: Sherry F. Lee, Kenneth R. Harris, David Joseph
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Patent number: 7673262Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.Type: GrantFiled: May 13, 2008Date of Patent: March 2, 2010Assignee: PDF Solutions, Inc.Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
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Publication number: 20080282210Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.Type: ApplicationFiled: May 13, 2008Publication date: November 13, 2008Applicant: PDF Solutions, Inc.Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
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Patent number: 7373625Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.Type: GrantFiled: August 10, 2006Date of Patent: May 13, 2008Assignee: PDF Solutions, Inc.Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
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Patent number: 7356800Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.Type: GrantFiled: August 10, 2006Date of Patent: April 8, 2008Assignee: PDF Solutions, Inc.Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
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Patent number: 7174521Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.Type: GrantFiled: March 10, 2005Date of Patent: February 6, 2007Assignee: PDF Solutions, Inc.Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
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Patent number: 6901564Abstract: A yield for an integrated circuit is predicted by processing a wafer to have a portion fabricated with at least one layout attribute of the integrated circuit. The portion of the wafer is analyzed to determine an actual yield associated with the at least one layout attribute. A systematic yield associated with the at least one layout attribute is determined based on the actual yield and a predicted yield associated with the at least one layout attribute. The predicted yield assumes that random defects are the only yield loss mechanism. A yield of an actual or proprosed product layout is predicted for the integrated circuit based on the systematic yield.Type: GrantFiled: July 18, 2002Date of Patent: May 31, 2005Assignee: PDF Solutions, Inc.Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
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Patent number: 6795952Abstract: A system and method for predicting yield of integrated circuits includes a characterization vehicle (12) having at least one feature representative of at least one type of feature to be incorporated in the final integrated circuit, preferably a device neighborhood, process neighborhood characterization vehicle. The characterization vehicle (12) is subjected to process operations making up the fabrication cycle to be used in fabricating the integrated circuit in order to produce a yield model (16). The yield model (16) embodies a layout as defined by the characterization vehicle (12) and preferably includes features which facilitates the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine (18) extracts predetermined layout attributes (26) from a proposed product layout (20).Type: GrantFiled: November 20, 2002Date of Patent: September 21, 2004Assignee: PDF Solutions, Inc.Inventors: Brian E. Stine, David M. Stashower, Sherry F. Lee, Kurt H. Weiner
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Publication number: 20030145292Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.Type: ApplicationFiled: July 18, 2002Publication date: July 31, 2003Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower