Patents by Inventor Shi-Bai Chen
Shi-Bai Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240136275Abstract: A semiconductor package structure includes a capacitor substrate and a first semiconductor die. The capacitor substrate has a first surface and a second surface opposite the first surface and includes a first redistribution structure, a second redistribution structure, a through via, and a first capacitor structure. The first redistribution structure is disposed on the first surface. The second redistribution structure is disposed on the second surface. The through via electrically couples the first redistribution structure to the second redistribution structure. The first capacitor structure is disposed between the first redistribution structure and the second redistribution structure and is electrically coupled to the second redistribution structure. The first semiconductor die is disposed over the capacitor substrate and is electrically coupled to the first capacitor structure through the second redistribution structure.Type: ApplicationFiled: September 21, 2023Publication date: April 25, 2024Inventors: Shi-Bai CHEN, Wei-Chih CHEN
-
Publication number: 20240038648Abstract: A semiconductor package includes a partitioned package substrate that is composed of multiple discrete substrates arranged in a side-by-side manner. The discrete substrates include a central substrate and peripheral substrates surrounding the central substrate. At least one integrated circuit die is mounted on a first surface of the partitioned package substrate. A plurality of solder balls is mounted on a second surface of the partitioned package substrate opposite to the first surface.Type: ApplicationFiled: June 29, 2023Publication date: February 1, 2024Applicant: MEDIATEK INC.Inventors: Wei-Chih Chen, Shi-Bai Chen
-
Publication number: 20240038647Abstract: A semiconductor package includes a partitioned package substrate composed of substrate parts arranged in a side-by-side manner; an integrated circuit die mounted on a first surface of the partitioned package substrate; and solder balls mounted on a second surface of the partitioned package substrate opposite to the first surface.Type: ApplicationFiled: June 29, 2023Publication date: February 1, 2024Applicant: MEDIATEK INC.Inventors: Wei-Chih Chen, Shi-Bai Chen
-
Patent number: 10910320Abstract: A shielded metal-oxide-metal (MOM) capacitor includes a substrate, a lower shielding plate disposed on the substrate and in parallel with a major surface of the substrate, an upper shielding plate situated above the lower shielding plate and in parallel with the lower shielding plate, and a middle plate sandwiched between the lower shielding plate and the upper shielding plate. The middle plate includes two parallel first connecting bars extending along a first direction, a plurality of first fingers extending between the two parallel first connecting bars along a second direction, and an electrode strip spaced apart from and surrounded by the two parallel first connecting bars and the first fingers.Type: GrantFiled: September 12, 2018Date of Patent: February 2, 2021Assignee: MEDIATEK INC.Inventor: Shi-Bai Chen
-
Publication number: 20190164903Abstract: A shielded metal-oxide-metal (MOM) capacitor includes a substrate, a lower shielding plate disposed on the substrate and in parallel with a major surface of the substrate, an upper shielding plate situated above the lower shielding plate and in parallel with the lower shielding plate, and a middle plate sandwiched between the lower shielding plate and the upper shielding plate. The middle plate includes two parallel first connecting bars extending along a first direction, a plurality of first fingers extending between the two parallel first connecting bars along a second direction, and an electrode strip spaced apart from and surrounded by the two parallel first connecting bars and the first fingers.Type: ApplicationFiled: September 12, 2018Publication date: May 30, 2019Inventor: Shi-Bai Chen
-
Publication number: 20160027772Abstract: An integrated capacitor includes a semiconductor substrate comprising a trench isolation area; a first interlayer dielectric (ILD) layer covering the trench isolation area; a first electrode plate comprising at least a first contact layer in the first ILD layer, wherein the contact layer is disposed directly on the trench isolation area; a second electrode plate in the first ILD layer; and a capacitor dielectric structure between the first electrode plate and the second electrode plate.Type: ApplicationFiled: July 22, 2014Publication date: January 28, 2016Inventors: Shi-Bai Chen, Tung-Hsing Lee
-
Patent number: 9099467Abstract: An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.Type: GrantFiled: December 16, 2013Date of Patent: August 4, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kong-Beng Thei, Chung Long Cheng, Chung-Shi Liu, Harry-Hak-Lay Chuang, Shien-Yang Wu, Shi-Bai Chen
-
Publication number: 20140218100Abstract: An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.Type: ApplicationFiled: December 16, 2013Publication date: August 7, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kong-Beng Thei, Chung Long Cheng, Chung-Shi Liu, Harry-Hak-Lay Chuang, Shien-Yang Wu, Shi-Bai Chen
-
Patent number: 8629050Abstract: An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.Type: GrantFiled: April 10, 2012Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kong-Beng Thei, Chung Long Cheng, Chung-Shi Liu, Harry-Hak-Lay Chuang, Shien-Yang Wu, Shi-Bai Chen
-
Patent number: 8361757Abstract: A semiconductor device assembly includes a first semiconductor die, a second semiconductor die, at least one semiconductor package component or another semiconductor die, a first conductive element and a second conductive element. The first semiconductor die includes at least one bonding pad. The second semiconductor die includes a bonding pad module. The first conductive element is coupled between the bonding pad module of the second semiconductor die and the bonding pad of the first semiconductor die, and the second conductive element is coupled between the bonding pad module of the second semiconductor die and the semiconductor package component or the another semiconductor die, wherein the first semiconductor die is coupled to the semiconductor package component or the another semiconductor die via the bonding pad and the bonding pad module and the first and second conductive elements.Type: GrantFiled: September 23, 2011Date of Patent: January 29, 2013Assignee: Mediatek Inc.Inventors: Yin-Chao Huang, Shi-Bai Chen, Kang-Wei Hsueh, Hung-Sung Li
-
Patent number: 8242586Abstract: An integrated circuit chip includes an analog and/or RF circuit block and a seal ring structure surrounding the analog and/or RF circuit block. The seal ring structure comprises a continuous outer seal ring and an inner seal ring, wherein the inner seal ring comprises a gap that is situated in front of the analog and/or RF circuit block.Type: GrantFiled: December 31, 2009Date of Patent: August 14, 2012Assignee: Mediatek Inc.Inventors: Tien-Chang Chang, Shi-Bai Chen, Tao Cheng, Yu-Hua Huang
-
Publication number: 20120196434Abstract: An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.Type: ApplicationFiled: April 10, 2012Publication date: August 2, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kong-Beng Thei, Chung Long Cheng, Chung-Shi Liu, Harry Chuang, Shien-Yang Wu, Shi-Bai Chen
-
Publication number: 20120154102Abstract: An electrical fuse structure includes a first metal strip having a first width W1 and a first length L1; a second metal strip having a second width W2 and a second length L2; and at least one via element having a via width W0, the via element being electrically connecting one end of the first metal strip to one end of the second metal strip, wherein W1<5W0.Type: ApplicationFiled: December 16, 2010Publication date: June 21, 2012Inventor: Shi-Bai Chen
-
Patent number: 8174091Abstract: An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.Type: GrantFiled: July 15, 2009Date of Patent: May 8, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kong-Beng Thei, Chung Long Cheng, Chung-Shi Liu, Harry Chuang, Shien-Yang Wu, Shi-Bai Chen
-
Publication number: 20120009734Abstract: A semiconductor device assembly includes a first semiconductor die, a second semiconductor die, at least one semiconductor package component or another semiconductor die, a first conductive element and a second conductive element. The first semiconductor die includes at least one bonding pad. The second semiconductor die includes a bonding pad module. The first conductive element is coupled between the bonding pad module of the second semiconductor die and the bonding pad of the first semiconductor die, and the second conductive element is coupled between the bonding pad module of the second semiconductor die and the semiconductor package component or the another semiconductor die, wherein the first semiconductor die is coupled to the semiconductor package component or the another semiconductor die via the bonding pad and the bonding pad module and the first and second conductive elements.Type: ApplicationFiled: September 23, 2011Publication date: January 12, 2012Inventors: Yin-Chao Huang, Shi-Bai Chen, Kang-Wei Hsueh, Hung-Sung Li
-
Patent number: 8049321Abstract: A semiconductor device assembly includes a first semiconductor die, a second semiconductor die, at least one semiconductor package component or another semiconductor die, a first conductive element and a second conductive element. The first semiconductor die includes at least one bonding pad. The second semiconductor die includes a bonding pad module. The first conductive element is coupled between the bonding pad module of the second semiconductor die and the bonding pad of the first semiconductor die, and the second conductive element is coupled between the bonding pad module of the second semiconductor die and the semiconductor package component or the another semiconductor die, wherein the first semiconductor die is coupled to the semiconductor package component or the another semiconductor die via the bonding pad and the bonding pad module and the first and second conductive elements.Type: GrantFiled: March 2, 2009Date of Patent: November 1, 2011Assignee: Mediatek Inc.Inventors: Yin-Chao Huang, Shi-Bai Chen, Kang-Wei Hsueh, Hung-Sung Li
-
Publication number: 20110108974Abstract: A packaged integrated circuit is provided comprising a first semiconductor die, a second semiconductor die, and a bonding wire. The first semiconductor die has a first internal bonding pad electrically connected to the package. The second semiconductor die has a second internal bonding pad located in an internal portion of the second semiconductor die. The second internal bonding pad is electrically connected to the first internal bonding pad through the first bonding wire.Type: ApplicationFiled: November 6, 2009Publication date: May 12, 2011Applicant: MEDIATEK INC.Inventors: Yin-Chao Huang, Shi-Bai Chen
-
Patent number: 7892895Abstract: System and method for providing an electrical fuse having a p-n junction diode. A preferred embodiment comprises a cathode, an anode, and one or more links formed between the cathode and the anode. The cathode and the portion of the cathode adjoining the link are doped with a first impurity, preferably a p-type impurity. The anode and the portion of the link adjoining the anode are doped with a second impurity, preferably an n-type impurity. The junction of the first impurity and the second impurity in the link forms a p-n junction diode. A conductive layer, such as a silicide layer, is formed over the p-n junction diodes. In an alternative embodiment, a plurality of p-n junction diodes may be formed in each link. One or more contacts may be formed to provide electrical contact to the cathode and the anode.Type: GrantFiled: August 19, 2005Date of Patent: February 22, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shien-Yang Wu, Shi-Bai Chen
-
Publication number: 20100102421Abstract: An integrated circuit chip includes an analog and/or RF circuit block and a seal ring structure surrounding the analog and/or RF circuit block. The seal ring structure comprises a continuous outer seal ring and an inner seal ring, wherein the inner seal ring comprises a gap that is situated in front of the analog and/or RF circuit block.Type: ApplicationFiled: December 31, 2009Publication date: April 29, 2010Inventors: Tien-Chang Chang, Shi-Bai Chen, Tao Cheng, Yu-Hua Huang
-
Publication number: 20100059867Abstract: An integrated circuit chip includes an analog and/or RF circuit block, a digital circuit, and a seal ring structure surrounding and protecting the analog and/or RF circuit block. The seal ring structure comprises a continuous outer seal ring, and a discontinuous inner seal ring divided into at least a first portion and a second portion. The second portion is situated in front of the analog and/or RF circuit block for shielding a noise from interfering the analog and/or RF circuit block.Type: ApplicationFiled: September 9, 2008Publication date: March 11, 2010Inventors: Tien-Chang Chang, Shi-Bai Chen, Tao Cheng