Abstract: Method for mitigating coherent noise and seismic data using an adaptively varying filter. The strongest and most coherent pattern (53), generally associated with the geology, is adaptively removed (56) from the original seismic data, producing an intermediate product that consists predominantly of noise. These noise data are then removed from the original input data (57) to produce a significantly more interpretable seismic volume.

Abstract: Systems and methods for facilitating passengers to manage airline reservations within electronic messages are disclosed. Interactive content may be determined based on airline reservation information associated with the passengers. The interactive content may include content sets for the passengers to purchase flight options such as upgrading seats, meals, entertainment, and the like within the electronic message. The interactive content may include content sets for the passengers to interact with (e.g., select) offers by merchants. Targeted offers or advertisements may be obtained from the merchants by providing passenger information. In some examples, selection of targeted offers for presentation to the passenger in the electronic messages may be made based on historical information related to the passenger (e.g., such as product preferences manifested by the passengers in the past).

Abstract: The present invention is related to microelectronic technologies, and discloses specifically a method of making a dynamic random access memory (DRAM) array. The DRAM array uses vertical MOS field effect transistors as array devices for the DRAM, and a buried metal silicide layer as buried bit lines for connecting multiple consecutive vertical MOS field effect transistor array devices. Each of the vertical MOS field-effect-transistor array devices includes a double gate structure with a buried layer of metal, which acts at the same time as buried word lines for the DRAM array. The DRAM array according to the present invention provides increased DRAM integration density, reduced buried bit line resistivity, and improved memory performance of the array devices.

Abstract: The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by concurrently formed metal-semiconductor compound contact regions at the source and drain and metal-semiconductor compounds in vias formed at positions corresponding to the source and drain. Because the metal-semiconductor compound has relatively low resistivity, the resistance of the metal-semiconductor compounds in the vias can be minimized. Also, because the material used to fill the vias and the material forming the source/drain contact regions are both metal-semiconductor compound, contact resistance between the material filling the vias and the metal-semiconductor compound source/drain contact regions can be minimized.

Abstract: A metal silicide thin film and ultra-shallow junctions and methods of making are disclosed. In the present disclosure, by using a metal and semiconductor dopant mixture as a target, a mixture film is formed on a semiconductor substrate using a physical vapor deposition (PVD) process. The mixture film is removed afterwards by wet etching, which is followed by annealing to form metal silicide thin film and ultra-shallow junctions. Because the metal and semiconductor dopant mixture is used as a target to deposit the mixture film, and the mixture film is removed by wet etching before annealing, self-limiting, ultra-thin, and uniform metal silicide film and ultra-shallow junctions are formed concurrently in semiconductor field-effect transistor fabrication processes, which are suitable for field-effect transistors at the 14 nm, 11 nm, or even further technology node.

Abstract: The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by forming vias or contact holes in an insulator layer covering the transistor and at metal silicide contact regions corresponding to the source and drain, and by filling the vias with metal-semiconductor compound. Because the metal-semiconductor compound has relatively low resistivity, the resistance of the material in the vias can be minimized. Also, because the material used to fill the vias and the material forming the source/drain contact regions are both metal-semiconductor compound, contact resistance between the material filling the vias and the source/drain contact regions can be minimized.

Abstract: The present invention provides a 6,13-dihalogen-5,14-dihydropentacene derivative and a method for production thereof. Compounds (b) and (c) are reacted through cross-coupling reaction in the presence of a metal compound and a lithiating agent to synthesize compound (d), which is then halogenated to thereby obtain a 6,13-dihalogen-5,14-dihydropentacene derivative (compound (e)). [wherein X1 and X2 are each a halogen atom, and R1, R2, R3, R4, R5, R6, R7, R8, R9 and R10 are each a hydrogen atom, an optionally substituted C1-C20 hydrocarbon group, etc.

Abstract: The present invention disclosure provides a super-long semiconductor nanowire structure. The super-long semiconductor nanowire structure is intermittently widened to prevent fractures in the super-long semiconductor nanowire structure. At the same time, the present invention further provides a method of making a super-long semiconductor nanowire structure. The method forms an intermittently widened super-long semiconductor nanowire structure using photolithography and etching. Because the super-long semiconductor nanowire structure is intermittently widened, fracturing of the super-long semiconductor nanowire structure during etching can be avoided, making it easier to form a super-long and ultra-thin semiconductor nanowire structure.

Abstract: The present invention provides a charge trapping non-volatile semiconductor memory device and a method of making the device. The charge trapping non-volatile semiconductor memory device comprises a semiconductor substrate, a source region, a drain region, and, consecutively formed over the semiconductor substrate, a channel insulation layer, a charge trapping layer, a blocking insulation layer, and a gate electrode. The drain region includes a P-N junction, and the source region includes a metal-semiconductor junction formed between the semiconductor substrate and a metal including titanium, cobalt, nickel, platinum or one of their various combinations. The charge trapping non-volatile semiconductor memory device according to the present disclosure has low programming voltage, fast programming speed, low energy consumption, and relatively high device reliability.

Abstract: The present invention belongs to the field of microelectronic device technologies. Specifically, an asymmetric source/drain field-effect transistor and its methods of making are disclosed. A structure of the field-effect transistor comprises: a semiconductor substrate, a gate structure, and a source region and a drain region having a mixed junction and a P-N junction, respectively. The source region and the drain region are asymmetrical structured with respect to each other, one of which comprises a P-N junction, and the other of which comprises a mixed junction, the mixed junction being a combination of a Schottky junction and a P-N junction. According to the present disclosure, a location of a doped region formed by ion implantation is controlled by adjusting an implantation angle, and a unique structure is formed for the asymmetric source/drain field-effect transistor.

Abstract: The present invention is related to microelectronic technologies, and discloses specifically a dynamic random access memory (DRAM) array and methods of making the same. The DRAM array uses vertical MOS field effect transistors as array devices for the DRAM, and a buried metal silicide layer as buried bit lines for connecting multiple consecutive vertical MOS field effect transistor array devices. Each of the vertical MOS field-effect-transistor array devices includes a double gate structure with a buried layer of metal, which acts at the same time as buried word lines for the DRAM array. The DRAM array according to the present invention provides increased DRAM integration density, reduced buried bit line resistivity, and improved memory performance of the array devices. The present invention also provides a method of making a DRAM array.

Abstract: The present invention provides a floating-gate non-volatile semiconductor memory device and a method of making the same. The floating-gate non-volatile semiconductor memory device comprises a semiconductor substrate, a source, a drain, a first insulator layer, a first polysilicon layer, a second insulator layer, a second polysilicon layer, a protective layer and sidewalls. The source and drain are disposed on the semiconductor substrate. The first insulator layer is disposed over a region of the semiconductor substrate other than regions corresponding to the source and drain. The first polysilicon layer is disposed over the first insulator layer, forming a floating gate. The second insulator layer is disposed over the first polysilicon layer. The second polysilicon layer is disposed over the second insulator layer, forming a control gate and a wordline. The sidewalls are disposed on two sides of the wordline, and the protective layer is disposed over the second polysilicon layer.

Abstract: The present invention provides a 6,13-dihalogen-5,14-dihydropentacene derivative and a method for production thereof. Compounds (b) and (c) are reacted through cross-coupling reaction in the presence of a metal compound and a lithiating agent to synthesize compound (d), which is then halogenated to thereby obtain a 6,13-dihalogen-5,14-dihydropentacene derivative (compound (e)). [wherein X1 and X2 are each a halogen atom, and R1, R2, R3, R4, R5, R6, R7, R8, R9 and R10 are each a hydrogen atom, an optionally substituted C1-C20 hydrocarbon group, etc.

Abstract: The present invention relates to the field of microelectronic technology. It discloses a mixed Schottky/P-N junction diode and a method of making the same. The mixed Schottky/P-N junction diode comprises a semiconductor substrate having a bulk region and a doped region, and a conductive layer on the semiconductor substrate. The doped region has opposite doping from that of the bulk region. A P-N junction is formed between the bulk region and the doped region, a Schottky junction is formed between the conductive layer and the semiconductor substrate, and an ohmic contact is formed between the conductive layer and the doped region. The mixed Schottky/P-N junction diode of the present invention has high operating current, fast switching speed, small leakage current, high breakdown voltage, ease of fabrication and other advantages.

Abstract: Disclosed herein is a method for preparing large soluble graphenes. The method comprises attaching one or more hindering groups to the graphene, which can prevent face-to-face graphene stacking by reducing the effects of inter-graphene attraction. The large graphenes can absorb a wide spectrum of light from UV to near infrared, and are useful in photovoltaic devices and sensitizers in nanocrystalline solar cells.

Abstract: The present invention provides a floating-gate non-volatile semiconductor memory device and a method of making the same. The floating-gate non-volatile semiconductor memory device comprises a semiconductor substrate, a source, a drain, a first insulator layer, a first polysilicon layer, a second insulator layer, a second polysilicon layer, a protective layer and sidewalls. The source and drain are disposed on the semiconductor substrate. The first insulator layer is disposed over a region of the semiconductor substrate other than regions corresponding to the source and drain. The first polysilicon layer is disposed over the first insulator layer, forming a floating gate. The second insulator layer is disposed over the first polysilicon layer. The second polysilicon layer is disposed over the second insulator layer, forming a control gate and a wordline. The sidewalls are disposed on two sides of the wordline, and the protective layer is disposed over the second polysilicon layer.

Abstract: The present invention is related to microelectronic technologies, and discloses specifically a mixed junction source/drain field-effect-transistor and methods of making the same. The field-effect-transistor with mixed junction source/drain comprises a semiconductor substrate, a gate structure, sidewalls, and source and drain regions having mixed junction structures, which are combinations of Schottky and P-N junctions. Compared with Schottky junction field-effect-transistors, the mixed junction source/drain field-effect-transistor described in the present invention has the characteristics of relatively low source/drain leakage. At the same time, this field-effect-transistor has lower source/drain series resistances than that associated with P-N junction field-effect-transistors.

Abstract: The present invention provides a charge trapping non-volatile semiconductor memory device and a method of making the device. The charge trapping non-volatile semiconductor memory device comprises a semiconductor substrate, a source region, a drain region, and, consecutively formed over the semiconductor substrate, a channel insulation layer, a charge trapping layer, a blocking insulation layer, and a gate electrode. The drain region includes a P-N junction, and the source region includes a metal-semiconductor junction formed between the semiconductor substrate and a metal including titanium, cobalt, nickel, platinum or one of their various combinations. The charge trapping non-volatile semiconductor memory device according to the present disclosure has low programming voltage, fast programming speed, low energy consumption, and relatively high device reliability.

Abstract: A system and method for power control for ASIC device is disclosed. According to an embodiment, the present invention provides a system for adjusting power consumption of an application specific integrated circuit (ASIC) device. The system includes a first buffer that is configured to receive and store data. For example, the first buffer can be characterized by a first buffer level. The method also includes a controller configured to generate a control signal. According to an embodiment, the controller is coupled to the first buffer. The system additionally includes a power supply component, which is configured to receive the control signal and to provide at least at a first voltage and a second voltage. For example, the first voltage and the second voltage are different.

Abstract: The present invention discloses a PCI Express interface and a method of signal processing, and particularly relates to the physical coding sub-layer that transmits data between physical media access layer and media access control layer of the PCI Express. The PCI express interface of present invention enables physical coding sub-layer to be able to receive or output 8-bit data as well as to receive or output 16-bit data by adding an input interface unit and an output interface unit in physical coding sub-layer, thereby the data formats of physical coding sub-layer and media access control layer are compatible; enables the physical coding sub-layer to be able to handle data with sampling errors during transmission from physical media access layer to physical coding sub-layer by adding data adjustment unit in the physical coding sub-layer and applying corresponding signal processing method, thereby it ensures the integrity of the data transmitted over physical coding sub-layer.