Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate structure disposed over and interleaved with the stack of semiconductor layers, the metal gate structure including a gate electrode disposed over a gate dielectric layer, a first isolation structure disposed adjacent to a first sidewall of the stack of semiconductor layers, where the gate dielectric layer fills space between the first isolation structure and the first sidewall of the stack of semiconductor layers, and a second isolation structure disposed adjacent to a second sidewall of the stack of semiconductor layers, where the gate electrode fills the space between the second isolation structure and the second sidewall of the stack of semiconductor layers.

Abstract: A method includes forming semiconductive sheets over a substrate and arranged in a vertical direction; forming source/drain regions on either side of each of the semiconductive sheets; forming first air gap inner spacers interleaving with the semiconductive sheets; forming a gate around each of the semiconductive sheets, wherein the first air gap inner spacers are laterally between the gate and a first one of the source/drain regions.

Abstract: A semiconductor package includes electric integrated circuit dies, photoelectric integrated circuit dies, and an inter-chip waveguide. The electric integrated circuit dies are laterally encapsulated by a first insulating encapsulant. The photoelectric integrated circuit dies are laterally encapsulated by a second insulating encapsulant. Each one of photoelectric integrated circuit dies includes an optical input/output terminal. The inter-chip waveguide is disposed over the second insulating encapsulant, wherein the photoelectric integrated circuit dies are optically communicated with each other through the inter-chip waveguide.

Abstract: Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. The methods described herein allow for complex shapes (e.g., “L-shaped”) to be etched into a multi-layered stack to form fins used in the formation of active regions of the GAA nanostructure transistor structures. In some embodiments, the active regions may be formed with a first channel width and a first source/drain region having a first width and a second channel width and a second source/drain region having a second width that is less than the first width.

Abstract: A cold insulation cup includes a cup body with a cup opening at both ends, an inner container, a first cup cover and a second cup cover. The inner container is arranged in the cup body, and one end of the inner container is provided with a cup opening. The first cup cover is detachably arranged at the cup opening at one end of the cold insulation cup, the second cup cover is detachably arranged at the cup opening at the other end of the cold insulation cup. An inner cavity of the inner container forms a first storage region, a second storage region is formed between an outer wall of the inner container and an inner wall of the cup body, one of the first and second storage regions is used for storing a refrigerated object, and the other one is used for storing a cold insulation medium.

Abstract: A first gate-all-around (GAA) transistor and a second GAA transistor may be formed on a substrate. The first GAA transistor includes at least one silicon plate, a first gate structure, a first source region, and a first drain region. The second GAA transistor includes at least one silicon-germanium plate, a second gate structure, a second source region, and a second drain region. The first GAA transistor may be an n-type field effect transistor, and the second GAA transistor may be a p-type field effect transistor. The gate electrodes of the first gate structure and the second gate structure may include a same conductive material. Each silicon plate and each silicon-germanium plate may be single crystalline and may have a same crystallographic orientation for each Miller index.

Abstract: Crystalline Forms of Compound (I): pharmaceutically acceptable salts thereof and solvates of any of the foregoing are disclosed. Pharmaceutical compositions comprising the same, methods of treating disorders and conditions associated with oncogenic KIT and PDGFRA alterations using the same, and methods for making Compound (I) and crystalline forms thereof are also disclosed.

Abstract: A light-emitting device includes a light-emitting laminated structure, a first electrode, and a second electrode. The first electrode has a reflection layer, an intermediate layer, and an electrically conductive layer. The intermediate layer includes a barrier layer having a first repeating paired layer unit and a second repeating paired layer unit, each of which has a platinum layer. The first repeating paired layer unit is closer to the electrically conductive layer than the second repeating paired layer unit, and a thickness of the platinum layer of the first repeating paired layer unit is greater than a thickness of the platinum layer of the second repeating paired layer unit.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and first channel structures and second channel structures formed over the substrate. The semiconductor structure also includes a dielectric fin structure formed between the first channel structures and the second channel structures. In addition, the dielectric fin structure includes a core portion and first connecting portions connected to the core portion. The semiconductor structure also includes a gate structure including a first portion. In addition, the first portion of the gate structure is formed around the first channel structures and covers the first connecting portions of the dielectric fin structure.

Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: detecting a status of a rewritable non-volatile memory module; and determining whether to perform a data refresh operation on the rewritable non-volatile memory module according to a first condition and a second condition. The first condition is related to a first physical unit in the rewritable non-volatile memory module. The second condition is related to a plurality of second physical units in the rewritable non-volatile memory module. The data refresh operation is configured to update data in the rewritable non-volatile memory module to reduce a bit error rate of the data.

Abstract: Methods and systems for improving fusion bonding are disclosed. Plasma treatment is performed on a substrate prior to the fusion bonding, which leaves residual charge on the substrate to be fusion bonded. The residual charge is usually dissipated through an electrically conductive silicone cushion on a loading pin. In the methods, the amount of residual voltage on a test silicon wafer is measured. If the residual voltage is too high, this indicates the usable lifetime of the silicone cushion has passed, and the electrically conductive silicone cushion is replaced. This ensures the continued dissipation of residual charge during use in production, improving the quality of fusion bonds between substrates.

Abstract: A device includes a transistor. The transistor includes a plurality of stacked channels, a source/drain region coupled to the stacked channels, and a gate metal wrapped around the stacked channels. The transistor includes a plurality of inner spacers, each inner spacer being positioned laterally between the gate metal and the source/drain region and including a gap and an inner spacer liner layer between the gate metal and the source/drain region.

Abstract: A semiconductor package includes a redistribution structure, a supporting layer, a semiconductor device, and a transition waveguide structure. The redistribution structure includes a plurality of connectors. The supporting layer is formed over the redistribution structure and disposed beside and between the plurality of connectors. The semiconductor device is disposed on the supporting layer and bonded to the plurality of connectors, wherein the semiconductor device includes a device waveguide. The transition waveguide structure is disposed on the supporting layer adjacent to the semiconductor device, wherein the transition waveguide structure is optically coupled to the device waveguide.

Abstract: A light-emitting diode (LED) packaging module includes a plurality of LED chips spaced apart from one another, an encapsulating layer that fills in a space among the LED chips, a light-transmitting layer disposed on the encapsulating layer, a wiring assembly disposed on and electrically connected to the LED chips, and an insulation component that covers the encapsulating layer and the wiring assembly. Each of the LED chips includes an electrode assembly including first and second electrodes. The light-transmitting layer includes a light-transmitting layer that has a light transmittance greater than that of the encapsulating layer.

Abstract: A package includes an electronic die, a photonic die underlying and electronically communicating with the electronic die, a lens disposed on the electronic die, and a prism structure disposed on the lens and optically coupled to the photonic die. The prism structure includes first and second polymer layers, the first polymer layer includes a first curved surface concaving toward the photonic die, the second polymer layer embedded in the first polymer layer includes a second curved surface substantially conforming to the first curved surface, and an outer sidewall of the second polymer layer substantially aligned with an outer sidewall of the first polymer layer.

Abstract: A light-emitting diode (LED) packaging module includes light-emitting units arranged in an array having m row(s) and n column(s), an encapsulating layer, and a wiring assembly, where m and n each independently represents a positive integer. Each of the light-emitting units includes LED chips each including a chip first surface, a chip second surface, a chip side surface, and an electrode assembly disposed on the chip second surface. The encapsulating layer covers the chip side surface and fills a space among the LED chips. The wiring assembly is disposed on the chip second surface and is electrically connected to the electrode assembly.

Abstract: A light-emitting device includes a number (N) of light-emitting units, a number (a) of first metal pads and a number (b) of second metal pads. Each of the light-emitting units includes a number (n) of light-emitting chips each having two distinct terminals, where N and n are integers and N>1, n>?3. The numbers (a) and (b) are integers and a>1, b>1, and the terminals of each of the light-emitting chips are electrically connected to a unique combination of one of the number (a) of first metal pads and a number (b) of second metal pads, respectively. The numbers (N), (n), (a) and (b) satisfy the equation: a*b=n*N.

Abstract: A package structure is provided. The package structure includes a semiconductor chip and a protective layer laterally surrounding the semiconductor chip. The package structure also includes a polymer-containing element over the protective layer. The protective layer is wider than the polymer-containing element.

Abstract: A heating device includes a resonant circuit, a detection unit and a control unit. The resonant circuit includes an inverter circuit and a resonant tank. The inverter circuit provides a resonant tank current and a resonant tank voltage. The resonant tank includes a heating coil, a resonant tank capacitor, a resonant tank equivalent inductor and a resonant tank equivalent resistor. The detection unit calculates an inductance of the resonant tank equivalent inductor according to a capacitance of the resonant tank capacitor, a resonant period and a first expression. The detection unit calculates a resistance of the resonant tank equivalent resistor according to the inductance of the resonant tank equivalent inductor, a time change value, a reference voltage value, a negative peak voltage value and a second expression.

Abstract: A semiconductor chip package may include a lead frame having a first surface and a second surface opposite to each other. A groove may be provided on the first surface of the lead frame and filled with an adhesive. A width of the groove is not greater than a width of the semiconductor chip. A semiconductor chip may be disposed over the groove and affixed to the lead frame through the adhesive in the groove. A carrier may be disposed on the second surface of the lead frame. A method for manufacturing the semiconductor chip package is also provided.