Patents by Inventor Shi Liu

Shi Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250070013
    Abstract: A semiconductor package includes a redistribution structure, a supporting layer, a semiconductor device, and a transition waveguide structure. The redistribution structure includes a plurality of connectors. The supporting layer is formed over the redistribution structure and disposed beside and between the plurality of connectors. The semiconductor device is disposed on the supporting layer and bonded to the plurality of connectors, wherein the semiconductor device includes a device waveguide. The transition waveguide structure is disposed on the supporting layer adjacent to the semiconductor device, wherein the transition waveguide structure is optically coupled to the device waveguide.
    Type: Application
    Filed: November 14, 2024
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Hsiu-Jen Lin, Ming-Che Ho, Yu-Hsiang Hu, Chewn-Pu Jou, Cheng-Tse Tang
  • Publication number: 20250063897
    Abstract: A display substrate and a preparation method thereof, and a display apparatus. The display substrate includes a base substrate, at least one insulating film layer disposed on the base substrate, and a first electrode disposed on a side of the at least one insulating film layer away from the base substrate; wherein a concave-convex structure is disposed on a side of the at least one insulating film layer away from the base substrate, and there is an overlapping area between an orthographic projection of the concave-convex structure on the base substrate and an orthographic projection of the first electrode on the base substrate.
    Type: Application
    Filed: October 31, 2024
    Publication date: February 20, 2025
    Inventors: Haitao HUANG, Chuanxiang XU, Yong YU, Huili WU, Zhao CUI, Wenqu LIU, Shi SHU, Lina JING, Detian MENG, Zibo NI
  • Publication number: 20250062127
    Abstract: A method of a semiconductor-on-insulator structure includes the following steps. A semiconductor donor substrate is provided. A first implantation process is performed to form an exfoliation layer of the semiconductor donor substrate with a first ion concentration. A second implantation process is performed on a perimeter region of the exfoliation layer to form a high concentration region of the exfoliation layer with a second ion concentration higher than the first ion concentration. The semiconductor donor substrate is bonded to a semiconductor handle substrate, so that the exfoliation layer with the high concentration region is bonded to the semiconductor handle substrate. An annealing process is performed to separate the exfoliation layer from the rest of the semiconductor donor substrate.
    Type: Application
    Filed: August 15, 2023
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Su-Chun Yang, Jui Hsuan Tsai, Jih-Churng Twu, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20250060542
    Abstract: A package includes an electronic die, a photonic die underlying and electronically communicating with the electronic die, a lens disposed on the electronic die, and a prism structure disposed on the lens and optically coupled to the photonic die. The prism structure includes first and second polymer layers, the first polymer layer includes a first curved surface concaving toward the photonic die, the second polymer layer embedded in the first polymer layer includes a second curved surface substantially conforming to the first curved surface, and an outer sidewall of the second polymer layer substantially aligned with an outer sidewall of the first polymer layer.
    Type: Application
    Filed: November 3, 2024
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Hsiang Hsu, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Chung-Ming Weng
  • Patent number: 12230597
    Abstract: A package structure is provided. The package structure includes a semiconductor chip and a protective layer laterally surrounding the semiconductor chip. The package structure also includes a polymer-containing element over the protective layer. The protective layer is wider than the polymer-containing element.
    Type: Grant
    Filed: June 16, 2023
    Date of Patent: February 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Chih-Chiang Tsao, Wei-Yu Chen, Hsiu-Jen Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Publication number: 20250053064
    Abstract: Optical devices and methods of manufacture are presented in which a non-linear material is deposited or otherwise placed. Once the non-linear material has been deposited, implantation regions are formed within the non-linear material using an implantation process. The implantation regions are removed using an etching process, and electrodes are formed to the remaining material.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 13, 2025
    Inventors: Su-Chun Yang, Chen Chiang Yu, Jui Hsuan Tsai, Jih-Churng Twu, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 12222545
    Abstract: An integrated circuit package and a method of forming the same are provided. The integrated circuit package includes a photonic integrated circuit die. The photonic integrated circuit die includes an optical coupler. The integrated circuit package further includes an encapsulant encapsulating the photonic integrated circuit die, a first redistribution structure over the photonic integrated circuit die and the encapsulant, and an opening extending through the first redistribution structure and exposing the optical coupler.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hsuan Tai, Chung-Ming Weng, Hung-Yi Kuo, Cheng-Chieh Hsieh, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 12218020
    Abstract: A semiconductor package includes a circuit structure, a first redistribution layer, a second redistribution layer, a first encapsulant, a bus die and a plurality of through vias. The first redistribution layer is disposed over the circuit structure. The second redistribution layer is disposed over the first redistribution layer. The first encapsulant is disposed between the first redistribution layer and the second redistribution layer. The through vias surround the bus die. The first encapsulant is extended along an entire sidewall of the bus die, and a first surface of the bus die is substantially coplanar with top surfaces of the first encapsulant and the plurality of through vias.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Yi Wu, Chen-Hua Yu, Chung-Shi Liu, Yu-Min Liang
  • Patent number: 12210200
    Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.
    Type: Grant
    Filed: February 26, 2024
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Publication number: 20250025518
    Abstract: Disclosed is the use of Bifidobacterium lactis BL-99 in the protection of cartilage. Provided in the present invention is the use of Bifidobacterium lactis in the preparation of a composition for protecting cartilage, wherein the Bifidobacterium lactis is Bifidobacterium lactis with the deposit number of CGMCC No. 15650. The Bifidobacterium lactis can promote the development of cartilage, increase cartilage density, protect cartilage from damage, promote cartilage repair and/or ameliorate cartilage damage, and is beneficial to cartilage health.
    Type: Application
    Filed: November 22, 2022
    Publication date: January 23, 2025
    Inventors: Wei-Lian Hung, Yujie Shi, Wei-Hsien Liu, Haotian Feng, Biao Liu, Wei Li, Qingshan Chen, Mingqiao Zhou
  • Publication number: 20250030651
    Abstract: The present disclosure provides an information processing method, apparatus, electronic device and storage medium. An information processing method comprises: in response to inputting first item information by a first user, storing the first item information in a first system and determining a first topic group based on the first item information; and generating first topic information based on the first item information, and sending the first topic information to the first topic group; wherein the first topic information is associated with the first item information. The present disclosure realizes aggregated display of information and facilitates message aggregation and processing by processing personnel.
    Type: Application
    Filed: October 2, 2024
    Publication date: January 23, 2025
    Inventors: Xinru ZHANG, Shi Qiu, Wenbin Zhang, Haibo Liu, Li Chen
  • Patent number: 12205923
    Abstract: A semiconductor device, a circuit board structure and a manufacturing forming thereof are provided. A circuit board structure includes a core layer, a first build-up layer and a second build-up layer. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The circuit board structure has a plurality of stress releasing trenches extending into the first build-up layer and the second build-up layer.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: January 21, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tin-Hao Kuo, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Yu-Chia Lai, Po-Yuan Teng
  • Publication number: 20250016964
    Abstract: A node unit includes a base plate, at least one function module, and a non-conductive coolant. The function module includes a heat-generating element, a heat-dissipating structure, and a pump. The heat-generating element is disposed on the base plate, the heat-dissipating structure is disposed on the heat-generating element, and the pump is disposed on the heat-dissipating structure. The base plate and the at least one function module are immersed in the non-conductive coolant. The pump is configured to drive the non-conductive coolant to flow into the heat-dissipating structure and discharge from the heat-dissipating structure. An electronic device and an immersion cooling type equipment are also mentioned.
    Type: Application
    Filed: September 1, 2023
    Publication date: January 9, 2025
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Yu-Wen Chung, Shun-Wei Yang, Heng-Yu Lee, Hao-Yuan Cheng, Chun-Shi Liu, Chia-Wei Chang
  • Publication number: 20250015278
    Abstract: Disclosed is an all-solid-state lithium battery, characterized in that an anode of the all-solid-state lithium battery comprises solid lithium metal, a solid-state electrolyte of the all-solid-state lithium battery comprises lithium lanthanum zirconium oxide, and a joint interface region between the anode and the solid-state electrolyte contains at least lithium nitride and lithium alloy.
    Type: Application
    Filed: September 15, 2023
    Publication date: January 9, 2025
    Applicant: CPC CORPORATION, TAIWAN
    Inventors: Shih-An LIU, Yu-Kai LIAO, Shu-Fen HU, Kevin IPUTERA, Ru-Shi LIU, Jui-Hsiung HUANG
  • Patent number: 12193168
    Abstract: Circuit board includes conductive plate, core dielectric layer, metallization layer, first build-up stack, second build-up stack. Conductive plate has channels extending from top surface to bottom surface. Core dielectric layer extends on covering top surface and side surfaces of conductive plate. Metallization layer extends on core dielectric layer and within channels of conductive plate. Core dielectric layer insulates metallization layer from conductive plate. First build-up stack is disposed on top surface of conductive plate and includes conductive layers alternately stacked with dielectric layers. Conductive layers electrically connect to metallization layer. Second build-up stack is disposed on bottom surface of conductive plate. Second build-up stack includes bottommost dielectric layer and bottommost conductive layer. Bottommost dielectric layer covers bottom surface of conductive plate.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: January 7, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Yi Wu, Chien-Hsun Lee, Chen-Hua Yu, Chung-Shi Liu
  • Patent number: 12183682
    Abstract: A semiconductor package is provided. The semiconductor package includes: semiconductor dies, separated from one another, and including die I/Os at their active sides; and a redistribution structure, disposed at the active sides of the semiconductor dies and connected to the die I/Os, wherein the redistribution structure includes first and second routing layers sequentially arranged along a direction away from the die I/Os, the first routing layer includes a ground plane and first signal lines laterally surrounded by and isolated from the first ground plane, the first signal lines connect to the die I/Os and rout the die I/Os from a central region to a peripheral region of the redistribution structure, the second routing layer includes second signal lines and ground lines, and the second signal lines and the ground lines respectively extend from a location in the peripheral region to another location in the peripheral region through the central region.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: December 31, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsun Chen, Chien-Hsun Lee, Chung-Shi Liu, Jiun-Yi Wu, Shou-Yi Wang, Tsung-Ding Wang
  • Patent number: 12176282
    Abstract: A manufacturing method of a semiconductor package includes the following steps. A supporting layer is formed over a redistribution structure. A first planarization process is performed over the supporting layer. A lower dielectric layer is formed over the supporting layer, wherein the lower dielectric layer includes a concave exposing a device mounting region of the supporting layer. A first sacrificial layer is formed over the supporting layer, wherein the sacrificial layer filling the concave. A second planarization process is performed over the lower dielectric layer and the first sacrificial layer. A transition waveguide provided over the lower dielectric layer. The first sacrificial layer is removed. A semiconductor device is mounted over the device mounting region, wherein the semiconductor device includes a device waveguide is optically coupled to the transition waveguide.
    Type: Grant
    Filed: March 27, 2023
    Date of Patent: December 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Hsiu-Jen Lin, Ming-Che Ho, Yu-Hsiang Hu, Chewn-Pu Jou, Cheng-Tse Tang
  • Patent number: 12170267
    Abstract: A structure includes core substrates attached to a first side of a redistribution structure, wherein the redistribution structure includes first conductive features and first dielectric layers, wherein each core substrate includes conductive pillars, wherein the conductive pillars of the core substrates physically and electrically contact first conductive features; an encapsulant extending over the first side of the redistribution structure, wherein the encapsulant extends along sidewalls of each core substrate; and an integrated device package connected to a second side of the redistribution structure.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: December 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Chung-Shi Liu
  • Patent number: 12165985
    Abstract: In accordance with some embodiments a via is formed over a semiconductor device, wherein the semiconductor device is encapsulated within an encapsulant 129. A metallization layer and a second via are formed over and in electrical connection with the first via, and the metallization layer and the second via are formed using the same seed layer. Embodiments include fully landed vias, partially landed vias in contact with the seed layer, and partially landed vias not in contact with the seed layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Chen-Hua Yu, Hui-Jung Tsai, Hung-Jui Kuo, Chung-Shi Liu, Han-Ping Pu, Ting-Chu Ko
  • Patent number: 12164158
    Abstract: A package includes an electronic die, a photonic die underlying and electronically communicating with the electronic die, a lens disposed on the electronic die, and a prism structure disposed on the lens and optically coupled to the photonic die. The prism structure includes first and second polymer layers, the first polymer layer includes a first curved surface concaving toward the photonic die, the second polymer layer embedded in the first polymer layer includes a second curved surface substantially conforming to the first curved surface, and an outer sidewall of the second polymer layer substantially aligned with an outer sidewall of the first polymer layer.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Hsiang Hsu, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Chung-Ming Weng