Patents by Inventor Shi Liu
Shi Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250233200Abstract: A solid lithium-ion battery includes a solid electrolyte and a cathode. The cathode, formed on the surface of the solid electrolyte, includes lithium-metal chloride. The cathode has an alloy and an artificial solid electrolyte interphase layer. Thus, an interface between the solid electrolyte and the cathode has better wettability.Type: ApplicationFiled: June 14, 2024Publication date: July 17, 2025Inventors: YU-KAI LIAO, SHU-FEN HU, RU-SHI LIU, SUNG-TING YAO
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Publication number: 20250233167Abstract: A lithium-oxygen primary battery features using a catalyst-free electrolyte. Further, a lithium metal on the negative electrode thereof is decreased to reduce the N/P ratio. Therefore, the lithium-oxygen primary battery of the present invention has a lower cost. The lithium-oxygen primary battery of the present invention has a gravimetric energy density much higher than that of the lithium-oxygen secondary battery.Type: ApplicationFiled: May 13, 2024Publication date: July 17, 2025Inventors: KEVIN IPUTERA, SHANG-YANG HUANG, RU-SHI LIU, SUNG-TING YAO
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Patent number: 12354924Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.Type: GrantFiled: April 10, 2024Date of Patent: July 8, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsun Chen, Yu-Ling Tsai, Jiun Yi Wu, Chien-Hsun Lee, Chung-Shi Liu
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Patent number: 12354969Abstract: A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.Type: GrantFiled: November 28, 2023Date of Patent: July 8, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun Yi Wu, Chen-Hua Yu, Chung-Shi Liu, Chien-Hsun Lee
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Patent number: 12356558Abstract: An electronic assembly includes a first wafer including a stack of alternating first dielectric layers and first circuit layers, a flexible structure including a second dielectric layer and a second circuit layer covered by the second dielectric layer, and a second wafer stacked upon the first wafer and including chip packages arranged in an array. The flexible structure includes a first region embedded in the first wafer and a second region connected to the first region and extending out from an edge of the first wafer. The chip packages are electrically coupled to the second circuit layer of the flexible structure through the first circuit layers of the first wafer.Type: GrantFiled: April 18, 2023Date of Patent: July 8, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jiun-Yi Wu, Chien-Hsun Lee, Chen-Hua Yu, Chung-Shi Liu
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Patent number: 12334446Abstract: A semiconductor structure includes a first redistribution structure, a first local interconnect component disposed on the first redistribution structure, and a first interconnect structure over a second side of the first local interconnect component. The first local interconnect component includes a first plurality of redistribution layers. The first plurality of redistribution layers includes a first plurality of conductive features on a first side of the first local interconnect component. Each of the first plurality of conductive features are coupled to respective conductive features of the first redistribution structure. The first interconnect structure includes a second plurality of conductive features and a third plurality of conductive features. The second plurality of conductive features are electrically coupled to the third plurality of conductive features through the first local interconnect component.Type: GrantFiled: June 17, 2024Date of Patent: June 17, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jiun Yi Wu, Chen-Hua Yu, Chung-Shi Liu
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Publication number: 20250192080Abstract: An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna.Type: ApplicationFiled: February 19, 2025Publication date: June 12, 2025Inventors: Chen-Hua Yu, Kai-Chiang Wu, Chung-Shi Liu, Shou Zen Chang, Chao-Wen Shih
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Patent number: 12300652Abstract: According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.Type: GrantFiled: January 3, 2024Date of Patent: May 13, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Hung Lin, Hsiu-Jen Lin, Ming-Da Cheng, Yu-Min Liang, Chen-Shien Chen, Chung-Shi Liu
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Patent number: 12300659Abstract: A method includes placing a first package component and a second package component over a carrier. The first conductive pillars of the first package component and second conductive pillars of the second package component face the carrier. The method further includes encapsulating the first package component and the second package component in an encapsulating material, de-bonding the first package component and the second package component from the carrier, planarizing the first conductive pillars, the second conductive pillars, and the encapsulating material, and forming redistribution lines to electrically couple to the first conductive pillars and the second conductive pillars.Type: GrantFiled: January 3, 2022Date of Patent: May 13, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Jui Huang, Chien Ling Hwang, Chih-Wei Lin, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu
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Publication number: 20250138345Abstract: An electro-optical device includes a waveguide and a first electrode and a second electrode. The first electrode and the second electrode at first and second sides of the waveguide, wherein the first electrode and the second electrode directly contact and extend beyond the first and second sides of the waveguide respectively.Type: ApplicationFiled: October 25, 2023Publication date: May 1, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shuen-Shin Liang, Tsung-Fu Tsai, Szu-Wei Lu, Chung-Shi Liu, Chen-Hua Yu
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Patent number: 12288729Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.Type: GrantFiled: February 7, 2024Date of Patent: April 29, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
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Publication number: 20250125208Abstract: A method of manufacturing a semiconductor package includes the following steps. A first redistribution layer structure is formed over a circuit board structure. A through via is formed over the first redistribution layer structure. A first die is mounted onto the first redistribution layer structure aside the through via. A first encapsulant is formed to encapsulate the first die and the through via, wherein surfaces of the first encapsulant, the first die and the through via are substantially coplanar.Type: ApplicationFiled: December 25, 2024Publication date: April 17, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun-Yi Wu, Chen-Hua Yu, Chung-Shi Liu, Yu-Min Liang
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Publication number: 20250126723Abstract: Circuit board includes conductive plate, core dielectric layer, metallization layer, first build-up stack, second build-up stack. Conductive plate has channels extending from top surface to bottom surface. Core dielectric layer extends on covering top surface and side surfaces of conductive plate. Metallization layer extends on core dielectric layer and within channels of conductive plate. Core dielectric layer insulates metallization layer from conductive plate. First build-up stack is disposed on top surface of conductive plate and includes conductive layers alternately stacked with dielectric layers. Conductive layers electrically connect to metallization layer. Second build-up stack is disposed on bottom surface of conductive plate. Second build-up stack includes bottommost dielectric layer and bottommost conductive layer. Bottommost dielectric layer covers bottom surface of conductive plate.Type: ApplicationFiled: December 19, 2024Publication date: April 17, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun-Yi Wu, Chien-Hsun Lee, Chen-Hua Yu, Chung-Shi Liu
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Publication number: 20250123458Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.Type: ApplicationFiled: December 18, 2024Publication date: April 17, 2025Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Patent number: 12266673Abstract: A semiconductor package includes electric integrated circuit dies, photoelectric integrated circuit dies, and an inter-chip waveguide. The electric integrated circuit dies are laterally encapsulated by a first insulating encapsulant. The photoelectric integrated circuit dies are laterally encapsulated by a second insulating encapsulant. Each one of photoelectric integrated circuit dies includes an optical input/output terminal. The inter-chip waveguide is disposed over the second insulating encapsulant, wherein the photoelectric integrated circuit dies are optically communicated with each other through the inter-chip waveguide.Type: GrantFiled: June 29, 2022Date of Patent: April 1, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Lun Chang, Ching-Hua Hsieh, Chung-Hao Tsai, Chung-Shi Liu, Chuei-Tang Wang, Hsiu-Jen Lin
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Patent number: 12266619Abstract: An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna.Type: GrantFiled: July 26, 2023Date of Patent: April 1, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Hua Yu, Kai-Chiang Wu, Chung-Shi Liu, Shou Zen Chang, Chao-Wen Shih
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Patent number: 12260669Abstract: A package includes a sensor die, and an encapsulating material encapsulating the sensor die therein. A top surface of the encapsulating material is substantially coplanar with or higher than a top surface of the sensor die. A plurality of sensing electrodes is higher than the sensor die and the encapsulating material. The plurality of sensing electrodes is arranged as a plurality of rows and columns, and the plurality of sensing electrodes is electrically coupled to the sensor die. A dielectric layer covers the plurality of sensing electrodes.Type: GrantFiled: July 7, 2023Date of Patent: March 25, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hua Chen, Yu-Feng Chen, Chung-Shi Liu, Chen-Hua Yu, Hao-Yi Tsai, Yu-Chih Huang
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Publication number: 20250096035Abstract: A composite wafer may be provided by: forming a layer stack including a carrier layer, an ion implantation layer, and a transfer material layer by implanting ions into a donor wafer; forming intersecting trenches through the transfer material layer, the ion implantation layer, and an upper portion of the carrier layer; attaching the layer stack to an acceptor wafer including a stack of a handle substrate and a first dielectric oxide layer by bonding the layer stack to the first dielectric oxide layer; and cleaving the layer stack at the ion implantation layer, whereby a composite wafer including the acceptor wafer and patterned portions of the transfer material layer is formed.Type: ApplicationFiled: September 20, 2023Publication date: March 20, 2025Inventors: Chen-Chiang Yu, Tsung-Fu Tsai, Szu-Wei Lu, Jih-Churng Twu, Chung-Shi Liu, Chen-Hua Yu
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Publication number: 20250096198Abstract: A semiconductor device, a circuit board structure and a manufacturing forming thereof are provided. A circuit board structure includes a core layer, a first build-up layer and a second build-up layer. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The circuit board structure has a plurality of stress releasing trenches extending into the first build-up layer and the second build-up layer.Type: ApplicationFiled: December 5, 2024Publication date: March 20, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tin-Hao Kuo, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Yu-Chia Lai, Po-Yuan Teng
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Patent number: 12255174Abstract: A package includes a package substrate, an interposer over and bonded to the package substrate, a first wafer over and bonding to the interposer, and a second wafer over and bonding to the first wafer. The first wafer has independent passive device dies therein. The second wafer has active device dies therein.Type: GrantFiled: June 30, 2022Date of Patent: March 18, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Kuo Lung Pan, Shu-Rong Chun, Chi-Hui Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu