Patents by Inventor Shi Liu
Shi Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12266673Abstract: A semiconductor package includes electric integrated circuit dies, photoelectric integrated circuit dies, and an inter-chip waveguide. The electric integrated circuit dies are laterally encapsulated by a first insulating encapsulant. The photoelectric integrated circuit dies are laterally encapsulated by a second insulating encapsulant. Each one of photoelectric integrated circuit dies includes an optical input/output terminal. The inter-chip waveguide is disposed over the second insulating encapsulant, wherein the photoelectric integrated circuit dies are optically communicated with each other through the inter-chip waveguide.Type: GrantFiled: June 29, 2022Date of Patent: April 1, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Lun Chang, Ching-Hua Hsieh, Chung-Hao Tsai, Chung-Shi Liu, Chuei-Tang Wang, Hsiu-Jen Lin
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Patent number: 12266619Abstract: An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna.Type: GrantFiled: July 26, 2023Date of Patent: April 1, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Hua Yu, Kai-Chiang Wu, Chung-Shi Liu, Shou Zen Chang, Chao-Wen Shih
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Patent number: 12258265Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first substrate including a first face and a second face opposite the first face. A second substrate is bonded to the first face of the first substrate such that the second face of the first substrate faces away from the second substrate. One or more recesses are arranged in the second face of the first substrate and are configured to compensate for thermal expansion or thermal contraction.Type: GrantFiled: July 18, 2023Date of Patent: March 25, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hang Chang, I-Shi Wang, Jen-Hao Liu
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Patent number: 12260669Abstract: A package includes a sensor die, and an encapsulating material encapsulating the sensor die therein. A top surface of the encapsulating material is substantially coplanar with or higher than a top surface of the sensor die. A plurality of sensing electrodes is higher than the sensor die and the encapsulating material. The plurality of sensing electrodes is arranged as a plurality of rows and columns, and the plurality of sensing electrodes is electrically coupled to the sensor die. A dielectric layer covers the plurality of sensing electrodes.Type: GrantFiled: July 7, 2023Date of Patent: March 25, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hua Chen, Yu-Feng Chen, Chung-Shi Liu, Chen-Hua Yu, Hao-Yi Tsai, Yu-Chih Huang
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Publication number: 20250096198Abstract: A semiconductor device, a circuit board structure and a manufacturing forming thereof are provided. A circuit board structure includes a core layer, a first build-up layer and a second build-up layer. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The circuit board structure has a plurality of stress releasing trenches extending into the first build-up layer and the second build-up layer.Type: ApplicationFiled: December 5, 2024Publication date: March 20, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tin-Hao Kuo, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Yu-Chia Lai, Po-Yuan Teng
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Publication number: 20250096035Abstract: A composite wafer may be provided by: forming a layer stack including a carrier layer, an ion implantation layer, and a transfer material layer by implanting ions into a donor wafer; forming intersecting trenches through the transfer material layer, the ion implantation layer, and an upper portion of the carrier layer; attaching the layer stack to an acceptor wafer including a stack of a handle substrate and a first dielectric oxide layer by bonding the layer stack to the first dielectric oxide layer; and cleaving the layer stack at the ion implantation layer, whereby a composite wafer including the acceptor wafer and patterned portions of the transfer material layer is formed.Type: ApplicationFiled: September 20, 2023Publication date: March 20, 2025Inventors: Chen-Chiang Yu, Tsung-Fu Tsai, Szu-Wei Lu, Jih-Churng Twu, Chung-Shi Liu, Chen-Hua Yu
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Publication number: 20250090677Abstract: Provided is an antigen-binding protein having the following properties: (a) specifically binding to CDH6, and (b) having the activity of being internalized into CDH6-expressing cells by binding to CDH6. Further provided an immunoconjugate comprising an antibody or antigen binding fragment thereof that specifically binds to CDH6 and has internalization activity, a pharmaceutical product comprising the immunoconjugate and having therapeutic effects on a tumor, a method for treating a tumor using the immunoconjugate or the pharmaceutical product, and the like.Type: ApplicationFiled: December 9, 2022Publication date: March 20, 2025Inventors: Xun MENG, Shu-Hui LIU, Jing SHI, Mingqiao WANG, Rong PAN, Yueyun JIANG, Yiqiang WANG, Zhaohui WANG
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Patent number: 12255174Abstract: A package includes a package substrate, an interposer over and bonded to the package substrate, a first wafer over and bonding to the interposer, and a second wafer over and bonding to the first wafer. The first wafer has independent passive device dies therein. The second wafer has active device dies therein.Type: GrantFiled: June 30, 2022Date of Patent: March 18, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Kuo Lung Pan, Shu-Rong Chun, Chi-Hui Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu
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Publication number: 20250089485Abstract: Provided are a display panel and a display apparatus, the display panel includes a substrate and a drive circuit layer, wherein the drive circuit layer includes a pixel circuit (P) arranged in an array, a plurality of first scan signal lines (G1) and a plurality of second scan signal lines (G2). The drive circuit layer includes a plurality of first discharge structures (E1) and/or a plurality of second discharge structures (E2). At least one first discharge structure (E1) is electrically connected to a first scan signal line (G1) and a second scan signal line (G2) respectively, and the first scan signal line (G1) and the second scan signal line (G2) electrically connected to the first discharge structure (E1) are electrically connected to the same row of pixel circuit.Type: ApplicationFiled: November 24, 2022Publication date: March 13, 2025Inventors: Xuehuan FENG, Yubao KONG, Hao LIU, Shi SUN
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Publication number: 20250087641Abstract: A structure includes core substrates attached to a first side of a redistribution structure, wherein the redistribution structure includes first conductive features and first dielectric layers, wherein each core substrate includes conductive pillars, wherein the conductive pillars of the core substrates physically and electrically contact first conductive features; an encapsulant extending over the first side of the redistribution structure, wherein the encapsulant extends along sidewalls of each core substrate; and an integrated device package connected to a second side of the redistribution structure.Type: ApplicationFiled: November 7, 2024Publication date: March 13, 2025Inventors: Jiun Yi Wu, Chen-Hua Yu, Chung-Shi Liu
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Publication number: 20250087615Abstract: A package structure includes at least one semiconductor die, a plurality of hollow cylinders, an insulating encapsulant, a redistribution layer and through holes. The plurality of hollow cylinders is surrounding the at least one semiconductor die. The insulating encapsulant has a top surface and a bottom surface opposite to the top surface, wherein the insulating encapsulant encapsulates the at least one semiconductor die and the plurality of hollow cylinders. The redistribution layer is disposed on the top surface of the insulant encapsulant and over the at least one semiconductor die. The through holes are penetrating through the plurality of hollow cylinders.Type: ApplicationFiled: November 21, 2024Publication date: March 13, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Tin-Hao Kuo
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Publication number: 20250079326Abstract: A semiconductor package is provided. The semiconductor package includes: semiconductor dies, separated from one another, and including die I/Os at their active sides; and a redistribution structure, disposed at the active sides of the semiconductor dies and connected to the die I/Os, wherein the redistribution structure includes first and second routing layers sequentially arranged along a direction away from the die I/Os, the first routing layer includes a ground plane and first signal lines laterally surrounded by and isolated from the first ground plane, the first signal lines connect to the die I/Os and rout the die I/Os from a central region to a peripheral region of the redistribution structure, the second routing layer includes second signal lines and ground lines, and the second signal lines and the ground lines respectively extend from a location in the peripheral region to another location in the peripheral region through the central region.Type: ApplicationFiled: November 20, 2024Publication date: March 6, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsun Chen, Chien-Hsun Lee, Chung-Shi Liu, Jiun-Yi Wu, Shou-Yi Wang, Tsung-Ding Wang
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Publication number: 20250076599Abstract: A device structure includes: an interposer including metal wiring structures and optical waveguides that are embedded in interlayer dielectric layers, wherein the interposer includes a stepped outer sidewall including an outermost vertical surface segment, a laterally-recessed sidewall segment that is laterally recessed relative to the outermost vertical surface segment, and a connecting horizontal surface segment that connects the outermost vertical surface segment and the laterally-recessed vertical sidewall segment; and a fiber access unit having a first end that is optically coupled to a subset of the optical waveguides through at least one optical glue portion that is interposed between the fiber access unit and the laterally-recessed sidewall segment of the stepped outer sidewall.Type: ApplicationFiled: September 5, 2023Publication date: March 6, 2025Inventors: Tsung-Fu Tsai, Chao-Jen Wang, Szu-Wei Lu, Chung-Shi Liu, Chen-Hua Yu
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Publication number: 20250070013Abstract: A semiconductor package includes a redistribution structure, a supporting layer, a semiconductor device, and a transition waveguide structure. The redistribution structure includes a plurality of connectors. The supporting layer is formed over the redistribution structure and disposed beside and between the plurality of connectors. The semiconductor device is disposed on the supporting layer and bonded to the plurality of connectors, wherein the semiconductor device includes a device waveguide. The transition waveguide structure is disposed on the supporting layer adjacent to the semiconductor device, wherein the transition waveguide structure is optically coupled to the device waveguide.Type: ApplicationFiled: November 14, 2024Publication date: February 27, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Hsiu-Jen Lin, Ming-Che Ho, Yu-Hsiang Hu, Chewn-Pu Jou, Cheng-Tse Tang
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Publication number: 20250063897Abstract: A display substrate and a preparation method thereof, and a display apparatus. The display substrate includes a base substrate, at least one insulating film layer disposed on the base substrate, and a first electrode disposed on a side of the at least one insulating film layer away from the base substrate; wherein a concave-convex structure is disposed on a side of the at least one insulating film layer away from the base substrate, and there is an overlapping area between an orthographic projection of the concave-convex structure on the base substrate and an orthographic projection of the first electrode on the base substrate.Type: ApplicationFiled: October 31, 2024Publication date: February 20, 2025Inventors: Haitao HUANG, Chuanxiang XU, Yong YU, Huili WU, Zhao CUI, Wenqu LIU, Shi SHU, Lina JING, Detian MENG, Zibo NI
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Publication number: 20250062127Abstract: A method of a semiconductor-on-insulator structure includes the following steps. A semiconductor donor substrate is provided. A first implantation process is performed to form an exfoliation layer of the semiconductor donor substrate with a first ion concentration. A second implantation process is performed on a perimeter region of the exfoliation layer to form a high concentration region of the exfoliation layer with a second ion concentration higher than the first ion concentration. The semiconductor donor substrate is bonded to a semiconductor handle substrate, so that the exfoliation layer with the high concentration region is bonded to the semiconductor handle substrate. An annealing process is performed to separate the exfoliation layer from the rest of the semiconductor donor substrate.Type: ApplicationFiled: August 15, 2023Publication date: February 20, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Chun Yang, Jui Hsuan Tsai, Jih-Churng Twu, Chung-Shi Liu, Chen-Hua Yu
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Publication number: 20250060542Abstract: A package includes an electronic die, a photonic die underlying and electronically communicating with the electronic die, a lens disposed on the electronic die, and a prism structure disposed on the lens and optically coupled to the photonic die. The prism structure includes first and second polymer layers, the first polymer layer includes a first curved surface concaving toward the photonic die, the second polymer layer embedded in the first polymer layer includes a second curved surface substantially conforming to the first curved surface, and an outer sidewall of the second polymer layer substantially aligned with an outer sidewall of the first polymer layer.Type: ApplicationFiled: November 3, 2024Publication date: February 20, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Che-Hsiang Hsu, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Chung-Ming Weng
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Patent number: 12230597Abstract: A package structure is provided. The package structure includes a semiconductor chip and a protective layer laterally surrounding the semiconductor chip. The package structure also includes a polymer-containing element over the protective layer. The protective layer is wider than the polymer-containing element.Type: GrantFiled: June 16, 2023Date of Patent: February 18, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Jan Pei, Chih-Chiang Tsao, Wei-Yu Chen, Hsiu-Jen Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
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Publication number: 20250053064Abstract: Optical devices and methods of manufacture are presented in which a non-linear material is deposited or otherwise placed. Once the non-linear material has been deposited, implantation regions are formed within the non-linear material using an implantation process. The implantation regions are removed using an etching process, and electrodes are formed to the remaining material.Type: ApplicationFiled: August 11, 2023Publication date: February 13, 2025Inventors: Su-Chun Yang, Chen Chiang Yu, Jui Hsuan Tsai, Jih-Churng Twu, Chung-Shi Liu, Chen-Hua Yu
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Patent number: 12222545Abstract: An integrated circuit package and a method of forming the same are provided. The integrated circuit package includes a photonic integrated circuit die. The photonic integrated circuit die includes an optical coupler. The integrated circuit package further includes an encapsulant encapsulating the photonic integrated circuit die, a first redistribution structure over the photonic integrated circuit die and the encapsulant, and an opening extending through the first redistribution structure and exposing the optical coupler.Type: GrantFiled: April 18, 2023Date of Patent: February 11, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hsuan Tai, Chung-Ming Weng, Hung-Yi Kuo, Cheng-Chieh Hsieh, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu