Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.

Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.

Abstract: Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices are disclosed. In some embodiments, a method of using a tool for processing semiconductor devices includes a tool with a second material disposed over a first material, and a plurality of apertures disposed within the first material and the second material. The second material comprises a higher reflectivity than the first material. Each of the apertures is adapted to retain a package component over a support during an exposure to energy.

Abstract: A semiconductor structure includes a die, a molding surrounding the die, and a polymer over the die and the molding. The die has a top surface. The molding has a top surface. The polymer has a first bottom surface contact the die and a second surface contacting the molding. The first bottom surface is at a level substantially same as the second bottom surface.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes: a substrate including a transistor, wherein the semiconductor device is surrounded by a seal ring; an interconnect structure over the transistor; a recess on a sidewall of the seal ring; a test pad in the interconnect structure, wherein the test pad extends from the interconnect structure to the recess of the seal ring.

Abstract: A process includes depositing an edge fill dielectric over a first workpiece and a device disposed thereon. The edge fill dielectric is patterned so that only the edge portions remain. A second dielectric material is formed over the first workpiece, device, and edge fill dielectric. A planarization process levels the second dielectric material and the device. A bonding layer is formed thereon and a second workpiece bonded thereto by a dielectric-to-dielectric bond.

Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.

Abstract: An embodiment includes a first package component including a first integrated circuit die and a first encapsulant at least partially surrounding the first integrated circuit die. The device also includes a redistribution structure on the first encapsulant and coupled to the first integrated circuit die. The device also includes a first thermal module coupled to the first integrated circuit die. The device also includes a second package component bonded to the first package component, the second package component including a power module attached to the first package component, the power module including active devices. The device also includes a second thermal module coupled to the power module. The device also includes a mechanical brace extending from a top surface of the second thermal module to a bottom surface of the first thermal module, the mechanical brace physically contacting the first thermal module and the second thermal module.

Abstract: A structure includes a first via and a first conductive line embedded in a first dielectric layer and spaced apart from each other by the first dielectric layer. A first metal pattern disposed on the first via and embedded in a second dielectric layer. A first conductive via disposed on the first conductive line and embedded in the second dielectric layer. The first metal pattern and the first conductive via are spaced apart from each other and are located on a first horizontal level, and the first metal pattern has an open ring shape. A second via disposed on the first metal pattern and embedded in a third dielectric layer. An inductor structure including the first via, the first metal pattern, and the second via.

Abstract: A semiconductor package includes a first integrated circuit, a plurality of second integrated circuits, at least one adhesion layer and a molding compound. The second integrated circuits are bonded onto the first integrated circuit. The at least one adhesion layer extends between the second integrated circuits and on sidewalls of the second integrated circuits. The molding compound extends between the second integrated circuits and on the at least one adhesion layer, wherein a surface of the at least one adhesion layer facing away from the first integrated circuit is substantially coplanar with a surface of the molding compound facing away from the first integrated circuit.

Abstract: A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.

Abstract: A display back plate and a display device are provided. The display back plate includes multiple display units on a base substrate, at least one display unit includes a pixel region for displaying image and a light transmissive region allowing light to transmit; the pixel region includes a first trace layer and a second trace layer disposed in different layers along a thickness direction of the base substrate; and the pixel region further includes a first dielectric layer and a second dielectric layer between the first trace layer and the second trace layer, a ratio of a thickness of the first trace layer to that of the second trace layer is greater than 5; a sum of a thickness of the first dielectric layer and a thickness of the second dielectric layer is greater than 3 ?m, and the thickness of the first dielectric layer is less than 2 ?m.

Abstract: A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.

Abstract: A method of manufacturing a semiconductor structure includes receiving a die comprising a top surface and a sacrificial layer covering the top surface; disposing a molding surrounding the die; removing the sacrificial layer from the die; disposing a polymer over the die and the molding, wherein the polymer has a first bottom surface contacting the die and a second bottom surface contacting the molding, and the first bottom surface is at a level substantially same as the second bottom surface.

Abstract: A semiconductor structure includes a first redistribution structure, a first local interconnect component disposed on the first redistribution structure, and a first interconnect structure over a second side of the first local interconnect component. The first local interconnect component includes a first plurality of redistribution layers. The first plurality of redistribution layers includes a first plurality of conductive features on a first side of the first local interconnect component. Each of the first plurality of conductive features are coupled to respective conductive features of the first redistribution structure. The first interconnect structure includes a second plurality of conductive features and a third plurality of conductive features. The second plurality of conductive features are electrically coupled to the third plurality of conductive features through the first local interconnect component.

Abstract: A counter substrate is provided. The counter substrate includes a bank layer on a base substrate and defining a plurality of bank apertures; a quantum dots material layer on the base substrate, the quantum dots material layer including a plurality of quantum dots blocks respectively in at least some of the plurality of bank apertures; and a support layer on a side of the quantum dots material layer and the bank layer away from the base substrate. The support layer includes one or more support portions, orthographic projections of which on the base substrate adjacent to a periphery of an orthographic projection of a respective one of the plurality of bank apertures on the base substrate. An orthographic projection of the bank layer on the base substrate at least partially overlaps with an orthographic projection of the support layer on the base substrate.

Abstract: Technologies described herein relate to conflict detection in a geo-replication architecture that includes several computing systems, where a database is asynchronously updated at the several computing systems and update notifications are transmitted amongst the computing systems to ensure that the database is replicated across the computing systems. Partial vector clocks, instead of full vector clocks, are used to update the database at different computing systems, thereby using fewer network resources when compared to conventional approaches. Further, less than whole vector clocks can be persisted with records stored on disk, thereby using fewer disk resources when compared with conventional approaches.

Abstract: The present invention discloses a recombinant RBD trimer protein capable of simultaneously generating cross neutralization activity for various severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2) epidemic strains. The RBD trimer protein is taken as an antigen and supplemented with an adjuvant to immunize an organism, so that a high-titer neutralizing antibody aiming at various SARS-CoV-2 epidemic strains can be generated at the same time, and the antibody has a certain broad-spectrum property and can be used for treating and/or preventing SARS-CoV-2 infection and/or coronavirus disease 2019.

Abstract: The invention discloses a blockchain-based intrusion detection system for railway signal, which is built on a blockchain's distributed chain structure, without a central, trusted control center. This design mitigates the vulnerabilities associated with centralized intrusion detection centers. Additionally, by utilizing a blockchain-based distributed structure, it also eliminates the risk of a single point of failure for the intrusion detection center. Moreover, the data within the blockchain-based intrusion detection system is highly resistant to malicious tampering. This is achieved by leveraging the consensus mechanism inherent in the blockchain, which can achieve consensus among intrusion detection nodes. The current invention solves the internal evil attacks and avoid the inability to reach consensus between nodes due to internal evil, thereby affecting the intrusion detection performance; at the same time, the intrusion detection model can resist external network attacks.

Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.